Build starting @ 2019-03-05T06:36:00.991381 Running make -C /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid run (with MAKEFLAGS=' -j --jobserver-fds=3,4') --------------------------------------------------------------------------- make[1]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make clean make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' rm -rf build run.ok cd clb && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' cd clb_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' cd iob && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' cd iob_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' cd mmcm && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' cd pll && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' cd ps7_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' cd bram && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' cd bram_block && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' cd bram_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' cd dsp && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' cd dsp_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' cd fifo_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' cd monitor && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' cd monitor_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' cd cfg_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' cd orphan_int_column && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' cd clk_hrow && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' cd clk_bufg && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make database make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' bash generate.sh build/tiles tiles ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate_tiles.tcl # source "$::env(FUZDIR)/util.tcl" ## proc min_ysite { duts_in_column } { ## # Given a list of sites, return the one with the lowest Y coordinate ## ## set min_dut_y 9999999 ## ## foreach dut $duts_in_column { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## if { $dut_y < $min_dut_y } { ## set selected_dut $dut ## set min_dut_y $dut_y ## } ## } ## return $selected_dut ## } ## proc group_dut_cols { duts ypitch } { ## # Group a list of sites into pitch sized buckets ## # Ex: IOBs occur 75 to a CMT column ## # Set pitch to 75 to get 0-74 in one bucket, 75-149 in a second, etc ## # X0Y0 {IOB_X0Y49 IOB_X0Y48 IOB_X0Y47 ... } ## # Anything with a different x is automatically in a different bucket ## ## # LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column) ## set dut_columns "" ## foreach dut $duts { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## # 75 per column => 0, 75, 150, etc ## set y_column [expr ($dut_y / $ypitch) * $ypitch] ## dict append dut_columns "X${dut_x}Y${y_column}" "$dut " ## } ## return $dut_columns ## } ## proc loc_dut_col_bels { dut_columns cellpre cellpost } { ## # set cellpre di ## ## # Pick the smallest Y in each column and LOC a cell to it ## # cells must be named like $cellpre[$dut_index] ## # Return the selected sites ## ## set ret_bels {} ## set dut_index 0 ## ## dict for {column duts_in_column} $dut_columns { ## set sel_bel_str [min_ysite $duts_in_column] ## set sel_bel [get_bels $sel_bel_str] ## if {"$sel_bel" == ""} {error "Bad bel $sel_bel from bel str $sel_bel_str"} ## set sel_site [get_sites -of_objects $sel_bel] ## if {"$sel_site" == ""} {error "Bad site $sel_site from bel $sel_bel"} ## ## set cell [get_cells $cellpre$dut_index$cellpost] ## puts "LOCing cell $cell to site $sel_site (from bel $sel_bel)" ## set_property LOC $sel_site $cell ## ## set dut_index [expr $dut_index + 1] ## lappend ret_bels $sel_bel ## } ## ## return $ret_bels ## } ## proc loc_dut_col_sites { dut_columns cellpre cellpost } { ## set bels [loc_dut_col_bels $dut_columns $cellpre $cellpost] ## set sites [get_sites -of_objects $bels] ## return $sites ## } ## proc make_io_pad_sites {} { ## # get all possible IOB pins ## foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { ## set site [get_sites -of_objects $pad] ## if {[llength $site] == 0} { ## continue ## } ## if [string match IOB33* [get_property SITE_TYPE $site]] { ## dict append io_pad_sites $site $pad ## } ## } ## return $io_pad_sites ## } ## proc make_iob_pads {} { ## set io_pad_sites [make_io_pad_sites] ## ## set iopad "" ## dict for {key value} $io_pad_sites { ## # Some sites have more than one pad? ## lappend iopad [lindex $value 0] ## } ## return $iopad ## } ## proc make_iob_sites {} { ## set io_pad_sites [make_io_pad_sites] ## ## set sites "" ## dict for {key value} $io_pad_sites { ## lappend sites $key ## } ## return $sites ## } ## proc assign_iobs_old {} { ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] ## } ## proc assign_iobs {} { ## # Set all I/Os on the bus to valid values somewhere on the chip ## # The iob fuzzer sets these to more specific values ## ## # All possible IOs ## set iopad [make_iob_pads] ## # Basic pins ## # XXX: not all pads are valid, but seems to be working for now ## # Maybe better to set to XRAY_PIN_* and take out of the list? ## set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb] ## ## # din bus ## set fixed_pins 3 ## set iports [get_ports di*] ## for {set i 0} {$i < [llength $iports]} {incr i} { ## set pad [lindex $iopad [expr $i+$fixed_pins]] ## set port [lindex $iports $i] ## set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port ## } ## } ## proc make_project {} { ## # Generate .bit only over ROI ## make_project_roi XRAY_ROI_TILEGRID ## } ## proc make_project_roi { roi_var } { ## # 6 CMTs in our reference part ## # What is the largest? ## set n_di 16 ## ## create_project -force -part $::env(XRAY_PART) design design ## ## read_verilog "$::env(FUZDIR)/top.v" ## synth_design -top top -verilog_define N_DI=$n_di ## ## assign_iobs ## ## create_pblock roi ## add_cells_to_pblock [get_pblocks roi] [get_cells roi] ## foreach roi "$::env($roi_var)" { ## puts "ROI: $roi" ## resize_pblock [get_pblocks roi] -add "$roi" ## } ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## set_param tcl.collectionResultDisplayLimit 0 ## ## set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## } # proc write_tiles_txt {} { # # Get all tiles, ie not just the selected LUTs # set tiles [get_tiles] # # # Write tiles.txt with site metadata # set fp [open "tiles.txt" w] # foreach tile $tiles { # set type [get_property TYPE $tile] # set grid_x [get_property GRID_POINT_X $tile] # set grid_y [get_property GRID_POINT_Y $tile] # set sites [get_sites -quiet -of_objects $tile] # set typed_sites {} # # if [llength $sites] { # set site_types [get_property SITE_TYPE $sites] # foreach t $site_types s $sites { # lappend typed_sites $t $s # } # } # # puts $fp "$type $tile $grid_x $grid_y $typed_sites" # } # close $fp # } # proc run {} { # # Generate grid of entire part # make_project_roi XRAY_ROI_TILEGRID # # place_design # route_design # write_checkpoint -force design.dcp # write_bitstream -force design.bit # # write_tiles_txt # } # run Command: synth_design -top top -verilog_define N_DI=16 Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15535 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 17260 ; free virtual = 51802 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] Parameter DIN_N bound to: 16 - type: integer Parameter DOUT_N bound to: 108 - type: integer INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-638] synthesizing module 'roi' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized0' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized1' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized2' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized3' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized4' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized5' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized7' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized7' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized8' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized9' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized9' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized10' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized10' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized11' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized11' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized12' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized12' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized13' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized13' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized14' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized14' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized15' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized15' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized16' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized16' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized17' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized17' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized18' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized18' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized19' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized19' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized20' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized20' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized21' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized21' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized22' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized22' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized23' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized23' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized24' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized24' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized25' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized25' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized26' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized26' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized27' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized27' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized28' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized28' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized29' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized29' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized30' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized30' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized31' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized31' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized32' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized32' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized33' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized33' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized34' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized34' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized35' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized35' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized36' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized36' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized37' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized37' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized38' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized38' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized39' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized39' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized40' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized40' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized41' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized41' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized42' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized42' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized43' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized43' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized44' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized44' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized45' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized45' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized46' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized46' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized47' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized47' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized48' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized48' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized49' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized49' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized50' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized50' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized51' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized51' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized52' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized52' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized53' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized53' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized54' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized54' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized55' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized55' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized56' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized56' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized57' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized57' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized58' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized58' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized59' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized59' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized60' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized60' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized61' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized61' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized62' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized62' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized63' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized63' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized64' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized64' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized65' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized65' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized66' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized66' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized67' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized67' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized68' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized68' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized69' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized69' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized70' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized70' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized71' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized71' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized72' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized72' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized73' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized73' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized74' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized74' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized75' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized75' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized76' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized76' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized77' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized77' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized78' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized78' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized79' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized79' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized80' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized80' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized81' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized81' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized82' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized82' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized83' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized83' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized84' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized84' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized85' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized85' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized86' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized86' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized87' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized87' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized88' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized88' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized89' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized89' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized90' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized90' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized91' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized91' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized92' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized92' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized93' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized93' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized94' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized94' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized95' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized95' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized96' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized96' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized97' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized97' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized98' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized98' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'RAMB36E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized0' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized3' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized4' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized5' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized6' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-256] done synthesizing module 'roi' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-256] done synthesizing module 'top' (5#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] WARNING: [Synth 8-3331] design roi has unconnected port clk --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 17263 ; free virtual = 51806 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 17264 ; free virtual = 51807 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 17264 ; free virtual = 51807 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'din_reg' and it is trimmed from '16' to '8' bits. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:36] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.949 ; gain = 110.508 ; free physical = 17257 ; free virtual = 51800 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (di_bufs[8].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[9].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[10].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[11].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[12].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[13].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[14].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[14]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[13]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[12]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[11]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[10]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[9]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[8]) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.918 ; gain = 233.477 ; free physical = 17095 ; free virtual = 51638 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.918 ; gain = 233.477 ; free physical = 17094 ; free virtual = 51637 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17093 ; free virtual = 51636 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 3| |2 |LUT3 | 108| |3 |LUT6 | 100| |4 |RAMB36E1 | 8| |5 |FDRE | 125| |6 |IBUF | 11| |7 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 356| |2 | roi |roi | 216| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17096 ; free virtual = 51639 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 96 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.934 ; gain = 243.492 ; free physical = 17097 ; free virtual = 51640 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.941 ; gain = 243.492 ; free physical = 17097 ; free virtual = 51640 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 230 Infos, 96 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1472.961 ; gain = 390.074 ; free physical = 17036 ; free virtual = 51579 ROI: SLICE_X0Y0:SLICE_X43Y99 ROI: RAMB18_X0Y0:RAMB18_X2Y39 ROI: RAMB36_X0Y0:RAMB36_X2Y19 ROI: DSP48_X0Y0:DSP48_X1Y39 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1536.992 ; gain = 0.000 ; free physical = 16964 ; free virtual = 51507 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17075422c Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1536.992 ; gain = 0.000 ; free physical = 16963 ; free virtual = 51506 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1922.480 ; gain = 0.000 ; free physical = 16647 ; free virtual = 51191 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196761f3e Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 16642 ; free virtual = 51185 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 16642 ; free virtual = 51185 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 16642 ; free virtual = 51185 Phase 1 Placer Initialization | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.496 ; gain = 417.504 ; free physical = 16642 ; free virtual = 51185 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18f2ccf33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16624 ; free virtual = 51167 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16624 ; free virtual = 51167 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16620 ; free virtual = 51164 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16622 ; free virtual = 51165 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16622 ; free virtual = 51165 Phase 3 Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16622 ; free virtual = 51165 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16622 ; free virtual = 51165 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21d012c21 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21d012c21 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1ce33f28d Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ce33f28d Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16623 ; free virtual = 51167 Ending Placer Task | Checksum: 14c774d33 Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.539 ; gain = 505.547 ; free physical = 16636 ; free virtual = 51179 240 Infos, 98 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 2042.539 ; gain = 569.578 ; free physical = 16636 ; free virtual = 51179 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9c4f4a11 ConstDB: 0 ShapeSum: b0280322 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2073.184 ; gain = 30.645 ; free physical = 16429 ; free virtual = 50973 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2079.172 ; gain = 36.633 ; free physical = 16398 ; free virtual = 50941 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f8e08080 Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2079.172 ; gain = 36.633 ; free physical = 16398 ; free virtual = 50941 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b8accb7e Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16388 ; free virtual = 50931 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: fc55de3b Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16392 ; free virtual = 50935 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16391 ; free virtual = 50935 Phase 4 Rip-up And Reroute | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16391 ; free virtual = 50935 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16391 ; free virtual = 50935 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16391 ; free virtual = 50935 Phase 6 Post Hold Fix | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16391 ; free virtual = 50935 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0324117 % Global Horizontal Routing Utilization = 0.0410751 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. Phase 7 Route finalize | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16391 ; free virtual = 50935 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16390 ; free virtual = 50933 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1323db277 Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16390 ; free virtual = 50933 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 2094.227 ; gain = 51.688 ; free physical = 16424 ; free virtual = 50968 Routing Is Done. 247 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2133.016 ; gain = 90.477 ; free physical = 16424 ; free virtual = 50967 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2133.016 ; gain = 0.000 ; free physical = 16422 ; free virtual = 50967 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:37:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 257 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2474.121 ; gain = 341.105 ; free physical = 16452 ; free virtual = 51000 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:37:20 2019... mkdir -p build/basicdb cd build && python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate.py \ --tiles /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/tiles.txt \ --out /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/basicdb/tilegrid.json cd iob && make cd iob_int && make cd monitor && make cd bram && make cd bram_block && make cd bram_int && make cd clb && make cd clb_int && make cd dsp && make cd fifo_int && make cd cfg_int && make cd monitor_int && make make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' GENERATE_ARGS="--oneval 1 --design params.csv --dframe 26 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 14 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 3] # set pin_str [lindex $line 4] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # gets $fp line # # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 2] # set pin_str [lindex $line 3] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17840 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17847 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17859 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17904 INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17927 INFO: Helper process launched with PID 17935 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17942 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17956 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18023 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18153 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18169 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18203 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 14761 ; free virtual = 49323 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.988 ; free physical = 14758 ; free virtual = 49320 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 14743 ; free virtual = 49305 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 14729 ; free virtual = 49291 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 14724 ; free virtual = 49286 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 14688 ; free virtual = 49250 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 14656 ; free virtual = 49218 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 14633 ; free virtual = 49194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 14574 ; free virtual = 49136 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 14529 ; free virtual = 49090 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 14467 ; free virtual = 49029 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] WARNING: [Synth 8-350] instance 'idelayctrl' of module 'IDELAYCTRL' requires 3 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y11' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y12' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y15' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y16' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y17' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y18' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y21' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y22' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y23' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y24' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y25' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y26' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y27' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] INFO: [Synth 8-256] done synthesizing module 'LUT6' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y28' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'dummy_lut' of module 'LUT6' requires 7 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y29' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y30' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y3' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y4' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y33' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y34' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y35' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y36' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y39' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y40' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y41' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y42' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y45' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y46' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y47' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y48' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y5' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y6' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y9' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y10' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y100' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y149' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y50' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y99' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y107' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y108' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y119' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y120' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y131' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y132' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y143' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y144' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y57' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y58' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y69' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y70' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y81' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y82' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y93' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y94' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y113' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y114' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y137' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y138' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y63' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y64' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y87' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y88' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y101' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y102' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y103' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y104' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y105' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 14430 ; free virtual = 48991 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] ---------------------------------------------------------------------------------WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 14460 ; free virtual = 49026 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 14452 ; free virtual = 49020 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 14447 ; free virtual = 49015 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14455 ; free virtual = 49019 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 14457 ; free virtual = 49020 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 14467 ; free virtual = 49030 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 14462 ; free virtual = 49026 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1205.957 ; gain = 110.508 ; free physical = 14466 ; free virtual = 49030 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 14472 ; free virtual = 49035 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : Report RTL Partitions: 8 Bit Registers := 2 +---Muxes : +-+--------------+------------+----------+ 2 Input 8 Bit Muxes := 1 | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.496 ; free physical = 14465 ; free virtual = 49033 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 14469 ; free virtual = 49032 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 14470 ; free virtual = 49033 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 14468 ; free virtual = 49031 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.496 ; free physical = 14454 ; free virtual = 49018 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] Start Loading Part and Timing Information --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:37] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] Loading part: xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string --------------------------------------------------------------------------------- Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.523 ; free physical = 14447 ; free virtual = 49010 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:81] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:146] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:229] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:286] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:395] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:535] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:618] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:727] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 14431 ; free virtual = 48995 --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2029] Report RTL Partitions: +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2055] | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2138] No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2719] Start Part Resource Summary WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2737] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5393] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5559] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 14406 ; free virtual = 48970 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5642] --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5808] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6057] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6223] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 14402 ; free virtual = 48966 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6306] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7053] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.523 ; free physical = 14391 ; free virtual = 48955 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 14391 ; free virtual = 48955 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 14340 ; free virtual = 48904 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2082] --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2501] Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 14274 ; free virtual = 48838 WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 14280 ; free virtual = 48844 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 14266 ; free virtual = 48830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 14272 ; free virtual = 48837 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.941 ; gain = 94.504 ; free physical = 14297 ; free virtual = 48861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 14296 ; free virtual = 48861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.969 ; gain = 102.531 ; free physical = 14292 ; free virtual = 48858 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14289 ; free virtual = 48858 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 14283 ; free virtual = 48855 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14281 ; free virtual = 48854 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 14272 ; free virtual = 48845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 14271 ; free virtual = 48845 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 14270 ; free virtual = 48835 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 14260 ; free virtual = 48825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 14261 ; free virtual = 48826 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 14253 ; free virtual = 48818 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] No constraint files found. WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] --------------------------------------------------------------------------------- INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1464] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 14197 ; free virtual = 48762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 14194 ; free virtual = 48759 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 13973 ; free virtual = 48538 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 13829 ; free virtual = 48394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 13789 ; free virtual = 48354 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 13789 ; free virtual = 48354 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 13269 ; free virtual = 47835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 13124 ; free virtual = 47690 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.926 ; gain = 232.477 ; free physical = 13084 ; free virtual = 47649 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.234 ; free physical = 13078 ; free virtual = 47644 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1327.926 ; gain = 232.477 ; free physical = 13065 ; free virtual = 47631 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 13056 ; free virtual = 47622 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.234 ; free physical = 13058 ; free virtual = 47623 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13058 ; free virtual = 47623 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13055 ; free virtual = 47620 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13051 ; free virtual = 47617 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 13042 ; free virtual = 47608 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 13042 ; free virtual = 47607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 13028 ; free virtual = 47595 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 13028 ; free virtual = 47595 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping Report RTL Partitions: --------------------------------------------------------------------------------- +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13025 ; free virtual = 47596 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 13025 ; free virtual = 47595 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.922 ; gain = 207.484 ; free physical = 13026 ; free virtual = 47591 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 13027 ; free virtual = 47593 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.922 ; gain = 207.484 ; free physical = 13027 ; free virtual = 47592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 13025 ; free virtual = 47592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 13023 ; free virtual = 47588 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 13024 ; free virtual = 47590 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 13020 ; free virtual = 47590 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13019 ; free virtual = 47585 Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 13019 ; free virtual = 47585 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13019 ; free virtual = 47585 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13016 ; free virtual = 47582 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 13018 ; free virtual = 47584 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13018 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13018 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13018 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13018 ; free virtual = 47583 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 13020 ; free virtual = 47586 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- No constraint files found. Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 13018 ; free virtual = 47583 --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 200| |3 |IBUF | 200| +------+-----------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 401| +------+---------+-------+------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13019 ; free virtual = 47584 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 13018 ; free virtual = 47583 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 402 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13007 ; free virtual = 47572 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.211 ; free physical = 13007 ; free virtual = 47572 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13008 ; free virtual = 47573 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13002 ; free virtual = 47568 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13007 ; free virtual = 47572 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.668 ; gain = 216.211 ; free physical = 13007 ; free virtual = 47572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13007 ; free virtual = 47572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13007 ; free virtual = 47573 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13007 ; free virtual = 47573 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 13006 ; free virtual = 47572 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1337.949 ; gain = 242.492 ; free physical = 13006 ; free virtual = 47571 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12994 ; free virtual = 47559 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I1 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I2 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I3 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I4 to constant 0 --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I5 to constant 0 Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12992 ; free virtual = 47557 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12987 ; free virtual = 47553 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12981 ; free virtual = 47546 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12979 ; free virtual = 47544 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12979 ; free virtual = 47544 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12978 ; free virtual = 47543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT6 | 1| |2 |IBUF | 96| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 97| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12978 ; free virtual = 47543 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12976 ; free virtual = 47541 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 12977 ; free virtual = 47542 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12959 ; free virtual = 47525 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12958 ; free virtual = 47523 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12956 ; free virtual = 47521 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12955 ; free virtual = 47521 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12955 ; free virtual = 47520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12954 ; free virtual = 47520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12953 ; free virtual = 47519 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 12950 ; free virtual = 47516 No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 12951 ; free virtual = 47516 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 12951 ; free virtual = 47516 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12934 ; free virtual = 47499 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12931 ; free virtual = 47496 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47496 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12931 ; free virtual = 47497 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12931 ; free virtual = 47497 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12931 ; free virtual = 47497 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12931 ; free virtual = 47497 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.898 ; gain = 215.461 ; free physical = 12931 ; free virtual = 47497 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12933 ; free virtual = 47498 --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.906 ; gain = 215.461 ; free physical = 12933 ; free virtual = 47498 Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 12935 ; free virtual = 47500 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 12936 ; free virtual = 47502 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 400 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12905 ; free virtual = 47470 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12905 ; free virtual = 47470 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12904 ; free virtual = 47469 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12903 ; free virtual = 47469 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12903 ; free virtual = 47469 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12903 ; free virtual = 47469 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12903 ; free virtual = 47468 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 12902 ; free virtual = 47467 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 12903 ; free virtual = 47469 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12885 ; free virtual = 47450 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12885 ; free virtual = 47450 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12882 ; free virtual = 47448 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12882 ; free virtual = 47447 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12882 ; free virtual = 47447 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12882 ; free virtual = 47447 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12881 ; free virtual = 47447 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 12879 ; free virtual = 47445 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 12880 ; free virtual = 47445 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12846 ; free virtual = 47411 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12845 ; free virtual = 47410 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12840 ; free virtual = 47406 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12840 ; free virtual = 47405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12839 ; free virtual = 47405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12838 ; free virtual = 47403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12838 ; free virtual = 47403 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 12835 ; free virtual = 47401 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 12837 ; free virtual = 47402 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 12673 ; free virtual = 47239 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 12651 ; free virtual = 47216 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12561 ; free virtual = 47126 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1395.723 ; gain = 312.828 ; free physical = 12291 ; free virtual = 46877 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12290 ; free virtual = 46875 --------------------------------------------------------------------------------- Looping LIOB33_X0Y1 0 IOB_X0Y1 {di[0]} key "IOB_X0Y1" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl" line 77) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:38:05 2019... Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12284 ; free virtual = 46869 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y0' at site IDELAY_X0Y0, Site IOB_X0Y0 is not bonded. Place terminal di[0] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y1' at site IDELAY_X0Y1, Site IOB_X0Y1 is not bonded. Place terminal di[14] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y2' at site IDELAY_X0Y2, Site IOB_X0Y2 is not bonded. Place terminal di[15] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y29' at site IDELAY_X0Y29, Site IOB_X0Y29 is not bonded. Place terminal di[30] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y3' at site IDELAY_X0Y3, Site IOB_X0Y3 is not bonded. Place terminal di[32] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y30' at site IDELAY_X0Y30, Site IOB_X0Y30 is not bonded. Place terminal di[31] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y31' at site IDELAY_X0Y31, Site IOB_X0Y31 is not bonded. Place terminal di[4] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y32' at site IDELAY_X0Y32, Site IOB_X0Y32 is not bonded. Place terminal di[5] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y33' at site IDELAY_X0Y33, Site IOB_X0Y33 is not bonded. Place terminal di[34] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y34' at site IDELAY_X0Y34, Site IOB_X0Y34 is not bonded. Place terminal di[35] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y35' at site IDELAY_X0Y35, Site IOB_X0Y35 is not bonded. Place terminal di[36] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y36' at site IDELAY_X0Y36, Site IOB_X0Y36 is not bonded. Place terminal di[37] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y38' at site IDELAY_X0Y38, Site IOB_X0Y38 is not bonded. Place terminal di[13] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y39' at site IDELAY_X0Y39, Site IOB_X0Y39 is not bonded. Place terminal di[38] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y4' at site IDELAY_X0Y4, Site IOB_X0Y4 is not bonded. Place terminal di[33] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y40' at site IDELAY_X0Y40, Site IOB_X0Y40 is not bonded. Place terminal di[39] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y41' at site IDELAY_X0Y41, Site IOB_X0Y41 is not bonded. Place terminal di[40] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y42' at site IDELAY_X0Y42, Site IOB_X0Y42 is not bonded. Place terminal di[41] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y43' at site IDELAY_X0Y43, Site IOB_X0Y43 is not bonded. Place terminal di[6] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y44' at site IDELAY_X0Y44, Site IOB_X0Y44 is not bonded. Place terminal di[7] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y45' at site IDELAY_X0Y45, Site IOB_X0Y45 is not bonded. Place terminal di[42] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y46' at site IDELAY_X0Y46, Site IOB_X0Y46 is not bonded. Place terminal di[43] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y47' at site IDELAY_X0Y47, Site IOB_X0Y47 is not bonded. Place terminal di[44] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y48' at site IDELAY_X0Y48, Site IOB_X0Y48 is not bonded. Place terminal di[45] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y49' at site IDELAY_X0Y49, Site IOB_X0Y49 is not bonded. Place terminal di[1] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y0' at site IDELAY_X1Y0, Site IOB_X1Y0 is not bonded. Place terminal di[50] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y1' at site IDELAY_X1Y1, Site IOB_X1Y1 is not bonded. Place terminal di[92] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y10' at site IDELAY_X1Y10, Site IOB_X1Y10 is not bonded. Place terminal di[193] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2335] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y11' at site IDELAY_X1Y11, Site IOB_X1Y11 is not bonded. Place terminal di[102] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1243] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y12' at site IDELAY_X1Y12, Site IOB_X1Y12 is not bonded. Place terminal di[103] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1255] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y13' at site IDELAY_X1Y13, Site IOB_X1Y13 is not bonded. Place terminal di[82] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12287 ; free virtual = 46873 --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y14' at site IDELAY_X1Y14, Site IOB_X1Y14 is not bonded. Place terminal di[83] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y15' at site IDELAY_X1Y15, Site IOB_X1Y15 is not bonded. Place terminal di[132] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1603] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y16' at site IDELAY_X1Y16, Site IOB_X1Y16 is not bonded. Place terminal di[133] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1615] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y17' at site IDELAY_X1Y17, Site IOB_X1Y17 is not bonded. Place terminal di[134] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1627] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y18' at site IDELAY_X1Y18, Site IOB_X1Y18 is not bonded. Place terminal di[135] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1639] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y19' at site IDELAY_X1Y19, Site IOB_X1Y19 is not bonded. Place terminal di[64] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y2' at site IDELAY_X1Y2, Site IOB_X1Y2 is not bonded. Place terminal di[93] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y20' at site IDELAY_X1Y20, Site IOB_X1Y20 is not bonded. Place terminal di[65] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y21' at site IDELAY_X1Y21, Site IOB_X1Y21 is not bonded. Place terminal di[136] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1651] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y22' at site IDELAY_X1Y22, Site IOB_X1Y22 is not bonded. Place terminal di[137] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1663] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y23' at site IDELAY_X1Y23, Site IOB_X1Y23 is not bonded. Place terminal di[138] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1675] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y24' at site IDELAY_X1Y24, Site IOB_X1Y24 is not bonded. Place terminal di[139] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1687] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y25' at site IDELAY_X1Y25, Site IOB_X1Y25 is not bonded. Place terminal di[140] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1699] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y26' at site IDELAY_X1Y26, Site IOB_X1Y26 is not bonded. Place terminal di[141] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1711] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y27' at site IDELAY_X1Y27, Site IOB_X1Y27 is not bonded. Place terminal di[142] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1723] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y28' at site IDELAY_X1Y28, Site IOB_X1Y28 is not bonded. Place terminal di[143] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1735] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y29' at site IDELAY_X1Y29, Site IOB_X1Y29 is not bonded. Place terminal di[144] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1747] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y3' at site IDELAY_X1Y3, Site IOB_X1Y3 is not bonded. Place terminal di[146] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1771] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y30' at site IDELAY_X1Y30, Site IOB_X1Y30 is not bonded. Place terminal di[145] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1759] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y31' at site IDELAY_X1Y31, Site IOB_X1Y31 is not bonded. Place terminal di[66] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y32' at site IDELAY_X1Y32, Site IOB_X1Y32 is not bonded. Place terminal di[67] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y33' at site IDELAY_X1Y33, Site IOB_X1Y33 is not bonded. Place terminal di[148] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1795] --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y34' at site IDELAY_X1Y34, Site IOB_X1Y34 is not bonded. Place terminal di[149] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1807] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y35' at site IDELAY_X1Y35, Site IOB_X1Y35 is not bonded. Place terminal di[150] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1819] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y36' at site IDELAY_X1Y36, Site IOB_X1Y36 is not bonded. Place terminal di[151] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1831] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y37' at site IDELAY_X1Y37, Site IOB_X1Y37 is not bonded. Place terminal di[86] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12293 ; free virtual = 46879 CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y38' at site IDELAY_X1Y38, Site IOB_X1Y38 is not bonded. Place terminal di[87] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y39' at site IDELAY_X1Y39, Site IOB_X1Y39 is not bonded. Place terminal di[152] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1843] --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y4' at site IDELAY_X1Y4, Site IOB_X1Y4 is not bonded. Place terminal di[147] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1783] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y40' at site IDELAY_X1Y40, Site IOB_X1Y40 is not bonded. Place terminal di[153] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1855] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y41' at site IDELAY_X1Y41, Site IOB_X1Y41 is not bonded. Place terminal di[154] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1867] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y42' at site IDELAY_X1Y42, Site IOB_X1Y42 is not bonded. Place terminal di[155] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1879] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y43' at site IDELAY_X1Y43, Site IOB_X1Y43 is not bonded. Place terminal di[68] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y44' at site IDELAY_X1Y44, Site IOB_X1Y44 is not bonded. Place terminal di[69] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y45' at site IDELAY_X1Y45, Site IOB_X1Y45 is not bonded. Place terminal di[156] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1891] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y46' at site IDELAY_X1Y46, Site IOB_X1Y46 is not bonded. Place terminal di[157] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1903] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y47' at site IDELAY_X1Y47, Site IOB_X1Y47 is not bonded. Place terminal di[158] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1915] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y48' at site IDELAY_X1Y48, Site IOB_X1Y48 is not bonded. Place terminal di[159] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1927] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y49' at site IDELAY_X1Y49, Site IOB_X1Y49 is not bonded. Place terminal di[53] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y5' at site IDELAY_X1Y5, Site IOB_X1Y5 is not bonded. Place terminal di[160] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1939] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y6' at site IDELAY_X1Y6, Site IOB_X1Y6 is not bonded. Place terminal di[161] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1951] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y7' at site IDELAY_X1Y7, Site IOB_X1Y7 is not bonded. Place terminal di[74] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12300 ; free virtual = 46886 --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y8' at site IDELAY_X1Y8, Site IOB_X1Y8 is not bonded. Place terminal di[75] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y9' at site IDELAY_X1Y9, Site IOB_X1Y9 is not bonded. Place terminal di[192] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2323] --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12315 ; free virtual = 46890 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 12325 ; free virtual = 46891 Report Cell Usage: --------------------------------------------------------------------------------- +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1398.691 ; gain = 315.797 ; free physical = 12325 ; free virtual = 46892 Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ Command: place_design --------------------------------------------------------------------------------- Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12325 ; free virtual = 46892 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 12332 ; free virtual = 46899 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 12334 ; free virtual = 46901 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' Makefile:57: recipe for target 'iob/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1420.941 ; gain = 338.047 ; free physical = 12703 ; free virtual = 47270 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 18 Infos, 200 Warnings, 75 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1399.684 ; gain = 316.797 ; free physical = 12725 ; free virtual = 47292 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 12733 ; free virtual = 47300 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [DRC 23-27] Running DRC with 8 threads Looping INT_L_X0Y0 0 IDELAY_X0Y0 IOB_X0Y0 {di[0]} key "IOB_X0Y0" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl" line 75) INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:38:05 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Makefile:60: recipe for target 'iob_int/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 13146 ; free virtual = 47732 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Starting Placer Task INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1401.922 ; gain = 319.039 ; free physical = 13162 ; free virtual = 47748 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 13159 ; free virtual = 47745 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 13159 ; free virtual = 47745 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.953 ; gain = 0.000 ; free physical = 13046 ; free virtual = 47632 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1465.953 ; gain = 0.000 ; free physical = 13045 ; free virtual = 47632 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 13055 ; free virtual = 47623 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 13055 ; free virtual = 47622 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Starting Placer Task Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.973 ; gain = 0.000 ; free physical = 13047 ; free virtual = 47615 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1484.973 ; gain = 0.000 ; free physical = 13047 ; free virtual = 47615 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 13045 ; free virtual = 47612 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 13045 ; free virtual = 47612 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1404.926 ; gain = 322.039 ; free physical = 13071 ; free virtual = 47638 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Starting Placer Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 13090 ; free virtual = 47657 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1583c4629 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 13122 ; free virtual = 47689 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 13127 ; free virtual = 47695 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 13001 ; free virtual = 47568 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 13003 ; free virtual = 47571 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 12993 ; free virtual = 47561 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 12994 ; free virtual = 47561 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 13017 ; free virtual = 47584 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 12889 ; free virtual = 47456 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 12887 ; free virtual = 47455 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:31 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 12781 ; free virtual = 47348 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 12554 ; free virtual = 47121 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 12548 ; free virtual = 47115 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 12534 ; free virtual = 47101 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1551.281 ; gain = 0.000 ; free physical = 12466 ; free virtual = 47033 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12463 ; free virtual = 47030 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1551.281 ; gain = 0.000 ; free physical = 12450 ; free virtual = 47018 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12323 ; free virtual = 46890 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12272 ; free virtual = 46839 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12268 ; free virtual = 46836 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12259 ; free virtual = 46826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12319 ; free virtual = 46887 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12317 ; free virtual = 46885 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12310 ; free virtual = 46878 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 12311 ; free virtual = 46878 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 12312 ; free virtual = 46879 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1815.441 ; gain = 0.000 ; free physical = 11783 ; free virtual = 46351 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1903.484 ; gain = 437.531 ; free physical = 11730 ; free virtual = 46297 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1903.484 ; gain = 437.531 ; free physical = 11721 ; free virtual = 46288 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1903.484 ; gain = 437.531 ; free physical = 11720 ; free virtual = 46287 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1903.484 ; gain = 437.531 ; free physical = 11719 ; free virtual = 46286 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1903.484 ; gain = 437.531 ; free physical = 11718 ; free virtual = 46285 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1903.484 ; gain = 437.531 ; free physical = 11711 ; free virtual = 46279 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1903.484 ; gain = 501.562 ; free physical = 11711 ; free virtual = 46278 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1815.207 ; gain = 0.000 ; free physical = 11187 ; free virtual = 45754 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 11110 ; free virtual = 45677 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 11077 ; free virtual = 45644 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 11075 ; free virtual = 45643 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 11075 ; free virtual = 45642 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 11073 ; free virtual = 45641 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1903.250 ; gain = 441.531 ; free physical = 11071 ; free virtual = 45638 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1903.250 ; gain = 505.562 ; free physical = 11049 ; free virtual = 45617 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 10355 ; free virtual = 44922 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.461 ; gain = 0.000 ; free physical = 10096 ; free virtual = 44664 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1842.211 ; gain = 0.000 ; free physical = 9951 ; free virtual = 44518 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b00cead Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9880 ; free virtual = 44447 Phase 1.3 Build Placer Netlist Model Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.445 ; gain = 0.000 ; free physical = 9879 ; free virtual = 44446 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.3 Build Placer Netlist Model | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9875 ; free virtual = 44442 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9868 ; free virtual = 44435 Phase 1 Placer Initialization | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9863 ; free virtual = 44431 Phase 2 Global Placement WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 9851 ; free virtual = 44418 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 9845 ; free virtual = 44412 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 9845 ; free virtual = 44412 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 9845 ; free virtual = 44412 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 9840 ; free virtual = 44408 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 9835 ; free virtual = 44402 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 9833 ; free virtual = 44400 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 9831 ; free virtual = 44398 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 9829 ; free virtual = 44396 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 9829 ; free virtual = 44396 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.488 ; gain = 581.562 ; free physical = 9829 ; free virtual = 44396 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.445 ; gain = 0.000 ; free physical = 9811 ; free virtual = 44378 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 9767 ; free virtual = 44334 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 9760 ; free virtual = 44327 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 9757 ; free virtual = 44325 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 9756 ; free virtual = 44324 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 9755 ; free virtual = 44322 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1930.254 ; gain = 467.531 ; free physical = 9755 ; free virtual = 44322 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.254 ; gain = 531.562 ; free physical = 9754 ; free virtual = 44321 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 9747 ; free virtual = 44314 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 9739 ; free virtual = 44307 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 9737 ; free virtual = 44304 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 9729 ; free virtual = 44296 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 9717 ; free virtual = 44284 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1990.488 ; gain = 518.531 ; free physical = 9706 ; free virtual = 44274 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.488 ; gain = 583.562 ; free physical = 9706 ; free virtual = 44274 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19523 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19901 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Timing 38-35] Done setting XDC timing constraints. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 9248 ; free virtual = 43816 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 9211 ; free virtual = 43779 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 9210 ; free virtual = 43777 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 9206 ; free virtual = 43774 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 9206 ; free virtual = 43773 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 9205 ; free virtual = 43772 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 9206 ; free virtual = 43773 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 9206 ; free virtual = 43773 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9194 ; free virtual = 43761 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9190 ; free virtual = 43758 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d4686e25 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9189 ; free virtual = 43756 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ae434bf0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9179 ; free virtual = 43746 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 177f7ac55 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9179 ; free virtual = 43746 Phase 3.5 Small Shape Detail Placement Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9180 ; free virtual = 43747 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9180 ; free virtual = 43748 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9177 ; free virtual = 43744 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9168 ; free virtual = 43735 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9168 ; free virtual = 43735 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9153 ; free virtual = 43721 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9153 ; free virtual = 43720 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9153 ; free virtual = 43720 Phase 3 Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9153 ; free virtual = 43721 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9155 ; free virtual = 43723 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9156 ; free virtual = 43723 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9144 ; free virtual = 43711 Phase 4.4 Final Placement Cleanup Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9145 ; free virtual = 43712 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9144 ; free virtual = 43712 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9144 ; free virtual = 43711 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9143 ; free virtual = 43711 Phase 4.4 Final Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9140 ; free virtual = 43708 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9140 ; free virtual = 43707 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9139 ; free virtual = 43706 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9153 ; free virtual = 43720 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9153 ; free virtual = 43720 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9152 ; free virtual = 43720 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9152 ; free virtual = 43719 Ending Placer Task | Checksum: 1c0d5e9dc Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9151 ; free virtual = 43719 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 9151 ; free virtual = 43719 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 9162 ; free virtual = 43730 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2035.551 ; gain = 614.609 ; free physical = 9162 ; free virtual = 43730 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: dc3640d2 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.770 ; gain = 0.000 ; free physical = 8255 ; free virtual = 42822 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 8208 ; free virtual = 42776 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8209 ; free virtual = 42776 --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.484 ; gain = 452.203 ; free physical = 8065 ; free virtual = 42633 Phase 1.3 Build Placer Netlist Model INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000001 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2636] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2719] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 8038 ; free virtual = 42606 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2776] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 8026 ; free virtual = 42594 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 8026 ; free virtual = 42594 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1205.953 ; gain = 110.508 ; free physical = 8006 ; free virtual = 42574 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 7845 ; free virtual = 42413 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 7825 ; free virtual = 42394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 7824 ; free virtual = 42393 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 7767 ; free virtual = 42335 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.484 ; gain = 452.203 ; free physical = 7673 ; free virtual = 42241 Phase 1.4 Constrain Clocks/Macros 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 7715 ; free virtual = 42284 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.484 ; gain = 452.203 ; free physical = 7716 ; free virtual = 42284 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2003.484 ; gain = 452.203 ; free physical = 7705 ; free virtual = 42273 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.859 ; gain = 0.000 ; free physical = 7647 ; free virtual = 42215 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1558.859 ; gain = 0.000 ; free physical = 7644 ; free virtual = 42212 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7579 ; free virtual = 42147 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1327.922 ; gain = 232.477 ; free physical = 7569 ; free virtual = 42137 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1327.922 ; gain = 232.477 ; free physical = 7567 ; free virtual = 42136 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7564 ; free virtual = 42132 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7563 ; free virtual = 42132 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7545 ; free virtual = 42113 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7535 ; free virtual = 42104 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7530 ; free virtual = 42099 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 7530 ; free virtual = 42098 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1337.945 ; gain = 242.492 ; free physical = 7531 ; free virtual = 42099 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.574 ; gain = 216.121 ; free physical = 7498 ; free virtual = 42067 --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.574 ; gain = 216.121 ; free physical = 7481 ; free virtual = 42049 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7477 ; free virtual = 42045 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7462 ; free virtual = 42030 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7455 ; free virtual = 42023 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7450 ; free virtual = 42018 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7448 ; free virtual = 42016 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7447 ; free virtual = 42015 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7446 ; free virtual = 42014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7446 ; free virtual = 42014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7446 ; free virtual = 42014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7446 ; free virtual = 42014 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7445 ; free virtual = 42013 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 7445 ; free virtual = 42013 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.566 ; gain = 225.105 ; free physical = 7446 ; free virtual = 42014 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7445 ; free virtual = 42013 INFO: [Project 1-571] Translating synthesized netlist Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7431 ; free virtual = 41999 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7432 ; free virtual = 42000 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7440 ; free virtual = 42008 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7440 ; free virtual = 42008 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7414 ; free virtual = 41982 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.527 ; gain = 540.246 ; free physical = 7428 ; free virtual = 41997 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.527 ; gain = 624.277 ; free physical = 7428 ; free virtual = 41997 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1420.938 ; gain = 338.047 ; free physical = 7357 ; free virtual = 41925 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.969 ; gain = 0.000 ; free physical = 7276 ; free virtual = 41844 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1484.969 ; gain = 0.000 ; free physical = 7276 ; free virtual = 41844 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 1416.598 ; gain = 333.703 ; free physical = 7242 ; free virtual = 41810 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.629 ; gain = 0.000 ; free physical = 7254 ; free virtual = 41822 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1482.629 ; gain = 0.000 ; free physical = 7253 ; free virtual = 41821 Phase 1 Build RT Design | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2055.168 ; gain = 119.668 ; free physical = 6792 ; free virtual = 41360 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.156 ; gain = 124.656 ; free physical = 6757 ; free virtual = 41326 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.156 ; gain = 124.656 ; free physical = 6757 ; free virtual = 41326 INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e90f676 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6752 ; free virtual = 41321 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6747 ; free virtual = 41316 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6747 ; free virtual = 41316 Phase 4 Rip-up And Reroute | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6747 ; free virtual = 41316 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6747 ; free virtual = 41316 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6747 ; free virtual = 41315 Phase 6 Post Hold Fix | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6747 ; free virtual = 41315 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.211 ; gain = 130.711 ; free physical = 6744 ; free virtual = 41312 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.211 ; gain = 132.711 ; free physical = 6742 ; free virtual = 41310 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.211 ; gain = 132.711 ; free physical = 6742 ; free virtual = 41310 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.211 ; gain = 132.711 ; free physical = 6775 ; free virtual = 41344 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2107.000 ; gain = 203.516 ; free physical = 6775 ; free virtual = 41343 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2107.000 ; gain = 0.000 ; free physical = 6776 ; free virtual = 41346 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1963.348 ; gain = 0.000 ; free physical = 6760 ; free virtual = 41328 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2054.934 ; gain = 119.668 ; free physical = 6697 ; free virtual = 41266 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2059.922 ; gain = 124.656 ; free physical = 6692 ; free virtual = 41260 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a00a49b6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2059.922 ; gain = 124.656 ; free physical = 6693 ; free virtual = 41261 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6705 ; free virtual = 41274 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6683 ; free virtual = 41251 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6669 ; free virtual = 41237 Phase 4 Rip-up And Reroute | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6669 ; free virtual = 41237 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6668 ; free virtual = 41237 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6668 ; free virtual = 41237 Phase 6 Post Hold Fix | Checksum: 1439f5939 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2065.977 ; gain = 130.711 ; free physical = 6668 ; free virtual = 41237 Phase 1 Build RT Design | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2055.938 ; gain = 93.668 ; free physical = 6674 ; free virtual = 41243 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.926 ; gain = 99.656 ; free physical = 6647 ; free virtual = 41216 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d50581c6 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.926 ; gain = 99.656 ; free physical = 6647 ; free virtual = 41216 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1439f5939 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.977 ; gain = 131.711 ; free physical = 6643 ; free virtual = 41212 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1439f5939 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2069.977 ; gain = 134.711 ; free physical = 6642 ; free virtual = 41210 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1439f5939 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2069.977 ; gain = 134.711 ; free physical = 6641 ; free virtual = 41210 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2069.977 ; gain = 134.711 ; free physical = 6674 ; free virtual = 41243 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2108.766 ; gain = 205.516 ; free physical = 6676 ; free virtual = 41244 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 6675 ; free virtual = 41245 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.172 ; gain = 43.668 ; free physical = 6672 ; free virtual = 41241 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.160 ; gain = 49.656 ; free physical = 6630 ; free virtual = 41199 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.160 ; gain = 49.656 ; free physical = 6629 ; free virtual = 41199 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6609 ; free virtual = 41178 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2051.391 ; gain = 492.531 ; free physical = 6566 ; free virtual = 41135 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3 Initial Routing | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6565 ; free virtual = 41134 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6581 ; free virtual = 41150 Phase 4 Rip-up And Reroute | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6581 ; free virtual = 41150 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6581 ; free virtual = 41150 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6580 ; free virtual = 41150 Phase 6 Post Hold Fix | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.980 ; gain = 105.711 ; free physical = 6580 ; free virtual = 41150 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.980 ; gain = 106.711 ; free physical = 6601 ; free virtual = 41170 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.980 ; gain = 109.711 ; free physical = 6598 ; free virtual = 41167 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 124d36534 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.980 ; gain = 109.711 ; free physical = 6597 ; free virtual = 41166 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.980 ; gain = 109.711 ; free physical = 6626 ; free virtual = 41195 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2110.770 ; gain = 180.516 ; free physical = 6625 ; free virtual = 41194 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2078.215 ; gain = 59.711 ; free physical = 6628 ; free virtual = 41197 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 6569 ; free virtual = 41140 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6561 ; free virtual = 41130 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6565 ; free virtual = 41134 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6572 ; free virtual = 41141 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6573 ; free virtual = 41142 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6572 ; free virtual = 41141 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6569 ; free virtual = 41138 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 6570 ; free virtual = 41139 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 6566 ; free virtual = 41135 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 6549 ; free virtual = 41118 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 6588 ; free virtual = 41157 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2121.004 ; gain = 134.516 ; free physical = 6590 ; free virtual = 41159 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2121.004 ; gain = 0.000 ; free physical = 6601 ; free virtual = 41172 Running DRC as a precondition to command write_bitstream INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.172 ; gain = 44.668 ; free physical = 6582 ; free virtual = 41151 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.160 ; gain = 51.656 ; free physical = 6531 ; free virtual = 41100 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.160 ; gain = 51.656 ; free physical = 6526 ; free virtual = 41095 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2085.465 ; gain = 62.961 ; free physical = 6471 ; free virtual = 41040 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6469 ; free virtual = 41039 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6462 ; free virtual = 41031 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6462 ; free virtual = 41031 Phase 5 Delay and Skew Optimization Phase 1 Build RT Design | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.953 ; gain = 42.668 ; free physical = 6460 ; free virtual = 41030 Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6459 ; free virtual = 41029 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6457 ; free virtual = 41027 Phase 6 Post Hold Fix | Checksum: 5700a6dd Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6430 ; free virtual = 40999 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 6400 ; free virtual = 40969 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: edf89240 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 6398 ; free virtual = 40968 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.465 ; gain = 64.961 ; free physical = 6388 ; free virtual = 40957 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2090.465 ; gain = 67.961 ; free physical = 6390 ; free virtual = 40960 Phase 9 Depositing Routes Loading data files... Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.465 ; gain = 67.961 ; free physical = 6383 ; free virtual = 40952 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.465 ; gain = 67.961 ; free physical = 6425 ; free virtual = 40995 Routing Is Done. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2129.254 ; gain = 138.766 ; free physical = 6428 ; free virtual = 40998 Writing placer database... Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.191 ; gain = 34.641 ; free physical = 6382 ; free virtual = 40952 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing XDEF routing. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2076.180 ; gain = 40.629 ; free physical = 6329 ; free virtual = 40900 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2076.180 ; gain = 40.629 ; free physical = 6328 ; free virtual = 40899 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.246 ; gain = 60.961 ; free physical = 6316 ; free virtual = 40888 Phase 3 Initial Routing Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2129.254 ; gain = 0.000 ; free physical = 6317 ; free virtual = 40889 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6237 ; free virtual = 40807 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6237 ; free virtual = 40807 Phase 4 Rip-up And Reroute | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6236 ; free virtual = 40806 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6237 ; free virtual = 40807 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6235 ; free virtual = 40805 Phase 6 Post Hold Fix | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6237 ; free virtual = 40807 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 7 Route finalize INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6249 ; free virtual = 40819 Phase 3 Initial Routing Phase 7 Route finalize | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 6233 ; free virtual = 40803 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 6228 ; free virtual = 40798 Phase 9 Depositing Routes Phase 1 Build RT Design | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6228 ; free virtual = 40798 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6180 ; free virtual = 40750 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6178 ; free virtual = 40748 Phase 9 Depositing Routes | Checksum: 1446d92b6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 6164 ; free virtual = 40734 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 6193 ; free virtual = 40763 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2130.035 ; gain = 135.766 ; free physical = 6189 ; free virtual = 40759 Writing placer database... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6129 ; free virtual = 40699 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6125 ; free virtual = 40695 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6125 ; free virtual = 40695 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6125 ; free virtual = 40695 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6125 ; free virtual = 40695 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6125 ; free virtual = 40695 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Phase 7 Route finalize Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.391 ; gain = 492.531 ; free physical = 6147 ; free virtual = 40718 Phase 1.4 Constrain Clocks/Macros Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Writing XDEF routing. Loading data files... Writing XDEF routing logical nets. Writing XDEF routing special nets. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Write XDEF Complete: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2130.035 ; gain = 0.000 ; free physical = 6127 ; free virtual = 40700 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6126 ; free virtual = 40700 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6133 ; free virtual = 40707 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6133 ; free virtual = 40706 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 6164 ; free virtual = 40738 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.023 ; gain = 99.473 ; free physical = 6164 ; free virtual = 40737 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Running DRC as a precondition to command write_bitstream Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2051.391 ; gain = 492.531 ; free physical = 6183 ; free virtual = 40757 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b9dafcfc Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6181 ; free virtual = 40755 Phase 3 Initial Routing Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2135.023 ; gain = 0.000 ; free physical = 6165 ; free virtual = 40740 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2051.391 ; gain = 492.531 ; free physical = 6060 ; free virtual = 40634 Phase 2 Final Placement Cleanup INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5884 ; free virtual = 40455 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5848 ; free virtual = 40419 Phase 4 Rip-up And Reroute | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5841 ; free virtual = 40412 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5836 ; free virtual = 40407 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5829 ; free virtual = 40400 Phase 6 Post Hold Fix | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5824 ; free virtual = 40395 Phase 7 Route finalize Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2051.391 ; gain = 492.531 ; free physical = 5804 ; free virtual = 40375 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5821 ; free virtual = 40392 Phase 8 Verifying routed nets Verification completed successfully INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 8 Verifying routed nets | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5817 ; free virtual = 40388 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5777 ; free virtual = 40347 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 5812 ; free virtual = 40383 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 5812 ; free virtual = 40383 INFO: [Timing 38-35] Done setting XDC timing constraints. Writing placer database... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.457 ; gain = 0.000 ; free physical = 5833 ; free virtual = 40404 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2051.391 ; gain = 492.531 ; free physical = 5823 ; free virtual = 40394 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2051.391 ; gain = 574.562 ; free physical = 5836 ; free virtual = 40407 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 5822 ; free virtual = 40395 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 5610 ; free virtual = 40181 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 5595 ; free virtual = 40167 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 5595 ; free virtual = 40166 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 5595 ; free virtual = 40166 Phase 2 Global Placement Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4816 ; free virtual = 39387 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4808 ; free virtual = 39380 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4795 ; free virtual = 39366 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4715 ; free virtual = 39287 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4715 ; free virtual = 39287 Phase 3.5 Small Shape Detail Placement INFO: [Timing 38-35] Done setting XDC timing constraints. Loading data files... Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.117 ; gain = 0.000 ; free physical = 4692 ; free virtual = 39264 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4652 ; free virtual = 39223 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4652 ; free virtual = 39223 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4651 ; free virtual = 39223 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4651 ; free virtual = 39222 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4626 ; free virtual = 39198 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4620 ; free virtual = 39191 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4619 ; free virtual = 39190 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4618 ; free virtual = 39190 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4618 ; free virtual = 39189 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2027.543 ; gain = 542.574 ; free physical = 4628 ; free virtual = 39200 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2027.543 ; gain = 606.605 ; free physical = 4628 ; free virtual = 39200 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.160 ; gain = 511.531 ; free physical = 4627 ; free virtual = 39198 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.160 ; gain = 511.531 ; free physical = 4621 ; free virtual = 39193 Phase 1.4 Constrain Clocks/Macros INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.160 ; gain = 511.531 ; free physical = 4623 ; free virtual = 39195 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.160 ; gain = 511.531 ; free physical = 4596 ; free virtual = 39167 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.160 ; gain = 511.531 ; free physical = 4561 ; free virtual = 39132 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.160 ; gain = 511.531 ; free physical = 4557 ; free virtual = 39129 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.160 ; gain = 577.562 ; free physical = 4556 ; free virtual = 39127 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Loading site data... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Loading route data... Processing options... Creating bitmap... Loading site data... Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading route data... Processing options... Creating bitmap... Creating bitstream... Creating bitstream... Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Writing bitstream ./design.bit... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2451.871 ; gain = 343.105 ; free physical = 3561 ; free virtual = 38140 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:39 2019... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 2450.105 ; gain = 343.105 ; free physical = 3581 ; free virtual = 38161 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:40 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK Creating bitstream... GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Loading route data... Processing options... Creating bitmap... Creating bitstream... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.289 ; gain = 38.762 ; free physical = 5609 ; free virtual = 40192 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.277 ; gain = 44.750 ; free physical = 5599 ; free virtual = 40182 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.277 ; gain = 44.750 ; free physical = 5599 ; free virtual = 40182 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5540 ; free virtual = 40123 Phase 3 Initial Routing 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 2453.875 ; gain = 343.105 ; free physical = 5547 ; free virtual = 40131 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:45 2019... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5618 ; free virtual = 40201 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5626 ; free virtual = 40210 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5626 ; free virtual = 40210 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5626 ; free virtual = 40210 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5626 ; free virtual = 40210 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5625 ; free virtual = 40209 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5694 ; free virtual = 40277 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5693 ; free virtual = 40276 Phase 9 Depositing Routes Writing bitstream ./design.bit... Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5697 ; free virtual = 40280 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.332 ; gain = 62.805 ; free physical = 5769 ; free virtual = 40352 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 2193.121 ; gain = 101.594 ; free physical = 5769 ; free virtual = 40352 Bitstream size: 4243411 bytes Config size: 1060815 words Writing placer database... Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. Writing bitstream ./design.bit... INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Creating bitstream... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.121 ; gain = 0.000 ; free physical = 7511 ; free virtual = 42130 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 2466.129 ; gain = 331.105 ; free physical = 7482 ; free virtual = 42078 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:51 2019... 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2461.109 ; gain = 340.105 ; free physical = 7501 ; free virtual = 42098 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:51 2019... Running DRC as a precondition to command write_bitstream INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2465.430 ; gain = 336.176 ; free physical = 8677 ; free virtual = 43274 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:51 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 Bitstream size: 4243411 bytes touch build/specimen_001/OK Config size: 1060815 words GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2469.141 ; gain = 339.105 ; free physical = 10837 ; free virtual = 45443 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:56 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:39:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading data files... 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2474.125 ; gain = 334.105 ; free physical = 11034 ; free virtual = 45640 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:39:56 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23010 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23011 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23085 Creating bitstream... Phase 1 Build RT Design | Checksum: e91ff6d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.074 ; gain = 51.668 ; free physical = 11839 ; free virtual = 46448 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e91ff6d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2145.062 ; gain = 61.656 ; free physical = 11759 ; free virtual = 46368 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e91ff6d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2145.062 ; gain = 61.656 ; free physical = 11782 ; free virtual = 46391 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11703 ; free virtual = 46311 Phase 3 Initial Routing Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11729 ; free virtual = 46339 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11720 ; free virtual = 46331 Phase 4 Rip-up And Reroute | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11724 ; free virtual = 46335 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11719 ; free virtual = 46331 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11722 ; free virtual = 46334 Phase 6 Post Hold Fix | Checksum: 18fae605e Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11733 ; free virtual = 46345 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11941 ; free virtual = 46554 Phase 8 Verifying routed nets Verification completed successfully Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 8 Verifying routed nets | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11995 ; free virtual = 46608 Phase 9 Depositing Routes INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 18fae605e Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11897 ; free virtual = 46510 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.492 ; gain = 97.086 ; free physical = 11940 ; free virtual = 46553 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2219.281 ; gain = 167.891 ; free physical = 11940 ; free virtual = 46553 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23145 INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23149 INFO: Helper process launched with PID 23158 Writing placer database... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11890 ; free virtual = 46509 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11877 ; free virtual = 46497 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.844 ; gain = 41.668 ; free physical = 11761 ; free virtual = 46392 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.832 ; gain = 47.656 ; free physical = 11727 ; free virtual = 46358 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d6a1f794 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.832 ; gain = 47.656 ; free physical = 11727 ; free virtual = 46358 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.188 ; gain = 42.645 ; free physical = 11686 ; free virtual = 46320 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.176 ; gain = 47.633 ; free physical = 11691 ; free virtual = 46325 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.176 ; gain = 47.633 ; free physical = 11693 ; free virtual = 46327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11711 ; free virtual = 46346 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11713 ; free virtual = 46348 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b1023f3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.137 ; gain = 59.961 ; free physical = 11707 ; free virtual = 46343 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11703 ; free virtual = 46341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11704 ; free virtual = 46341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11703 ; free virtual = 46340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11703 ; free virtual = 46340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11701 ; free virtual = 46338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11701 ; free virtual = 46338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11674 ; free virtual = 46312 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Writing XDEF routing. Phase 4.1 Global Iteration 0 | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11668 ; free virtual = 46306 Phase 4 Rip-up And Reroute | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11665 ; free virtual = 46304 Phase 5 Delay and Skew Optimization Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 5 Delay and Skew Optimization | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11661 ; free virtual = 46300 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11658 ; free virtual = 46297 Phase 6 Post Hold Fix | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11648 ; free virtual = 46287 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:40:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 7 Route finalize 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 2532.727 ; gain = 339.605 ; free physical = 11644 ; free virtual = 46284 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:40:15 2019... Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2219.281 ; gain = 0.000 ; free physical = 11634 ; free virtual = 46275 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11631 ; free virtual = 46272 Phase 3 Initial Routing Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.137 ; gain = 60.961 ; free physical = 11634 ; free virtual = 46275 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.137 ; gain = 63.961 ; free physical = 11630 ; free virtual = 46271 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1b1023f3e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.137 ; gain = 63.961 ; free physical = 11609 ; free virtual = 46250 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.137 ; gain = 63.961 ; free physical = 11647 ; free virtual = 46289 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.926 ; gain = 134.766 ; free physical = 11647 ; free virtual = 46288 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11652 ; free virtual = 46294 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11666 ; free virtual = 46308 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11665 ; free virtual = 46307 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11666 ; free virtual = 46308 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11666 ; free virtual = 46308 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11666 ; free virtual = 46308 Writing placer database... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Writing XDEF routing. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11851 ; free virtual = 46495 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 11851 ; free virtual = 46495 Phase 9 Depositing Routes Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 12037 ; free virtual = 46682 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2095.230 ; gain = 67.688 ; free physical = 12070 ; free virtual = 46715 Routing Is Done. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2128.926 ; gain = 0.000 ; free physical = 12294 ; free virtual = 46939 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2134.020 ; gain = 106.477 ; free physical = 12293 ; free virtual = 46939 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 12595 ; free virtual = 47241 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2134.020 ; gain = 0.000 ; free physical = 12612 ; free virtual = 47260 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 12414 ; free virtual = 47032 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 12427 ; free virtual = 47046 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12428 ; free virtual = 47046 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- INFO: Helper process launched with PID 23378 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12436 ; free virtual = 47054 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23407 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 12098 ; free virtual = 46716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 12015 ; free virtual = 46633 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 11954 ; free virtual = 46572 --------------------------------------------------------------------------------- Loading data files... Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11854 ; free virtual = 46476 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11817 ; free virtual = 46435 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11812 ; free virtual = 46431 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] No constraint files found. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11803 ; free virtual = 46422 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11786 ; free virtual = 46405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11785 ; free virtual = 46403 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11778 ; free virtual = 46397 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11791 ; free virtual = 46409 Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11792 ; free virtual = 46411 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11793 ; free virtual = 46413 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11790 ; free virtual = 46409 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11753 ; free virtual = 46372 --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. Start Loading Part and Timing Information --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. Loading part: xc7z020clg400-1 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11752 ; free virtual = 46371 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11771 ; free virtual = 46394 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11755 ; free virtual = 46375 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11698 ; free virtual = 46318 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11696 ; free virtual = 46315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11677 ; free virtual = 46297 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11613 ; free virtual = 46232 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11610 ; free virtual = 46230 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11609 ; free virtual = 46228 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11607 ; free virtual = 46227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11605 ; free virtual = 46225 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11604 ; free virtual = 46224 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11601 ; free virtual = 46221 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11597 ; free virtual = 46216 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11598 ; free virtual = 46217 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11572 ; free virtual = 46191 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11568 ; free virtual = 46188 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11565 ; free virtual = 46185 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11565 ; free virtual = 46184 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11561 ; free virtual = 46181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11561 ; free virtual = 46180 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11556 ; free virtual = 46176 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11551 ; free virtual = 46170 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11549 ; free virtual = 46169 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11300 ; free virtual = 45919 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11302 ; free virtual = 45921 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11292 ; free virtual = 45912 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11100 ; free virtual = 45719 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 11101 ; free virtual = 45720 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11096 ; free virtual = 45715 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11094 ; free virtual = 45714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11092 ; free virtual = 45711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11092 ; free virtual = 45711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11091 ; free virtual = 45711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11091 ; free virtual = 45710 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11089 ; free virtual = 45708 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 11090 ; free virtual = 45710 INFO: [Project 1-571] Translating synthesized netlist INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading data files... 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 10955 ; free virtual = 45574 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 10951 ; free virtual = 45570 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 10880 ; free virtual = 45500 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 10880 ; free virtual = 45500 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 10772 ; free virtual = 45391 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 10672 ; free virtual = 45300 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 10672 ; free virtual = 45300 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 10677 ; free virtual = 45297 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 10560 ; free virtual = 45180 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 10560 ; free virtual = 45180 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10573 ; free virtual = 45194 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 10545 ; free virtual = 45165 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 10522 ; free virtual = 45143 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 10477 ; free virtual = 45102 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10444 ; free virtual = 45064 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10442 ; free virtual = 45063 Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10442 ; free virtual = 45062 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 10346 ; free virtual = 44967 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10166 ; free virtual = 44786 --------------------------------------------------------------------------------- Loading route data... Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10165 ; free virtual = 44785 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10171 ; free virtual = 44792 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10163 ; free virtual = 44783 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10162 ; free virtual = 44782 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10161 ; free virtual = 44781 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10160 ; free virtual = 44780 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 10159 ; free virtual = 44779 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 10161 ; free virtual = 44781 INFO: [Project 1-571] Translating synthesized netlist Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1398.688 ; gain = 315.797 ; free physical = 10137 ; free virtual = 44757 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10143 ; free virtual = 44763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 10140 ; free virtual = 44760 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10115 ; free virtual = 44736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10108 ; free virtual = 44729 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 10108 ; free virtual = 44728 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10097 ; free virtual = 44718 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10035 ; free virtual = 44656 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10035 ; free virtual = 44656 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10029 ; free virtual = 44650 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10027 ; free virtual = 44648 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10026 ; free virtual = 44646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10026 ; free virtual = 44646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10026 ; free virtual = 44646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10026 ; free virtual = 44646 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10026 ; free virtual = 44646 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10026 ; free virtual = 44646 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 10027 ; free virtual = 44647 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9999 ; free virtual = 44619 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9997 ; free virtual = 44618 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9997 ; free virtual = 44617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9997 ; free virtual = 44617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9997 ; free virtual = 44617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9997 ; free virtual = 44617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9996 ; free virtual = 44616 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9996 ; free virtual = 44616 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 9998 ; free virtual = 44618 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1398.684 ; gain = 315.797 ; free physical = 9939 ; free virtual = 44564 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 9977 ; free virtual = 44602 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 9970 ; free virtual = 44595 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 9970 ; free virtual = 44595 Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 9935 ; free virtual = 44560 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9920 ; free virtual = 44544 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23571 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9724 ; free virtual = 44349 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9720 ; free virtual = 44344 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9718 ; free virtual = 44342 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9715 ; free virtual = 44340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9715 ; free virtual = 44340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9714 ; free virtual = 44338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9714 ; free virtual = 44338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ No constraint files found. Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9714 ; free virtual = 44338 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9713 ; free virtual = 44337 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 9709 ; free virtual = 44334 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 9710 ; free virtual = 44334 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9690 ; free virtual = 44315 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Creating bitstream... --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:40:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2466.125 ; gain = 332.105 ; free physical = 9675 ; free virtual = 44299 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:40:41 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 10018 ; free virtual = 44642 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 10705 ; free virtual = 45330 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_002/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. #of segments: 2 #of bits: 388 #of tags: 1 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10677 ; free virtual = 45301 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10677 ; free virtual = 45301 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10675 ; free virtual = 45299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10674 ; free virtual = 45299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10675 ; free virtual = 45299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10674 ; free virtual = 45298 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10673 ; free virtual = 45297 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 10668 ; free virtual = 45292 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 10669 ; free virtual = 45293 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 10609 ; free virtual = 45233 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 10605 ; free virtual = 45229 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 10598 ; free virtual = 45222 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 10591 ; free virtual = 45216 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 10535 ; free virtual = 45164 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 10592 ; free virtual = 45222 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:40:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.031 ; gain = 341.105 ; free physical = 10600 ; free virtual = 45229 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:40:49 2019... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 11427 ; free virtual = 46058 Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 11426 ; free virtual = 46057 touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d7f8aeb2 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 11431 ; free virtual = 46062 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 11428 ; free virtual = 46059 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 11156 ; free virtual = 45787 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 11128 ; free virtual = 45759 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 11112 ; free virtual = 45743 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 11104 ; free virtual = 45735 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 11104 ; free virtual = 45735 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 11104 ; free virtual = 45735 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 11103 ; free virtual = 45734 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 11103 ; free virtual = 45734 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 11103 ; free virtual = 45734 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 10955 ; free virtual = 45590 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11038 ; free virtual = 45674 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11074 ; free virtual = 45710 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11075 ; free virtual = 45711 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11078 ; free virtual = 45714 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11079 ; free virtual = 45715 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 11106 ; free virtual = 45742 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 11107 ; free virtual = 45743 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1842.207 ; gain = 0.000 ; free physical = 10864 ; free virtual = 45500 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 466.531 ; free physical = 10804 ; free virtual = 45440 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 466.531 ; free physical = 10795 ; free virtual = 45431 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 466.531 ; free physical = 10789 ; free virtual = 45425 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 466.531 ; free physical = 10784 ; free virtual = 45420 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 466.531 ; free physical = 10778 ; free virtual = 45414 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1930.250 ; gain = 466.531 ; free physical = 10778 ; free virtual = 45414 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1930.250 ; gain = 531.562 ; free physical = 10777 ; free virtual = 45413 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:40:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:16] 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:40 . Memory (MB): peak = 2608.441 ; gain = 389.160 ; free physical = 10784 ; free virtual = 45420 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:40:56 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11831 ; free virtual = 46468 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11734 ; free virtual = 46371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 11732 ; free virtual = 46368 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1842.203 ; gain = 0.000 ; free physical = 11236 ; free virtual = 45878 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 11207 ; free virtual = 45849 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 11031 ; free virtual = 45673 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 11030 ; free virtual = 45672 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 11029 ; free virtual = 45672 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 11029 ; free virtual = 45672 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 11043 ; free virtual = 45686 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1930.246 ; gain = 467.531 ; free physical = 11059 ; free virtual = 45701 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1930.246 ; gain = 531.562 ; free physical = 11059 ; free virtual = 45701 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 10431 ; free virtual = 45073 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10367 ; free virtual = 45009 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 10326 ; free virtual = 44968 Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10323 ; free virtual = 44965 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10313 ; free virtual = 44955 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10309 ; free virtual = 44951 Phase 2 Final Placement Cleanup Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10305 ; free virtual = 44947 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 10303 ; free virtual = 44945 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 10303 ; free virtual = 44945 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10198 ; free virtual = 44840 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10169 ; free virtual = 44811 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10173 ; free virtual = 44815 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10170 ; free virtual = 44812 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10167 ; free virtual = 44809 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10166 ; free virtual = 44808 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 10166 ; free virtual = 44808 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24094 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 10042 ; free virtual = 44684 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 10051 ; free virtual = 44693 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9967 ; free virtual = 44609 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9695 ; free virtual = 44337 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9689 ; free virtual = 44331 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9677 ; free virtual = 44319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9673 ; free virtual = 44315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9673 ; free virtual = 44315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9671 ; free virtual = 44313 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9671 ; free virtual = 44313 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [Timing 38-35] Done setting XDC timing constraints. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9669 ; free virtual = 44311 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 9671 ; free virtual = 44313 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 9641 ; free virtual = 44283 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9625 ; free virtual = 44267 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9597 ; free virtual = 44240 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9580 ; free virtual = 44222 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9564 ; free virtual = 44206 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9548 ; free virtual = 44190 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 9529 ; free virtual = 44171 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 9526 ; free virtual = 44168 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 9324 ; free virtual = 43967 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ddcd7ec8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9286 ; free virtual = 43928 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9226 ; free virtual = 43868 Phase 1.4 Constrain Clocks/Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.4 Constrain Clocks/Macros | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9221 ; free virtual = 43863 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Starting Routing Task Phase 1 Placer Initialization | Checksum: 2751fe4ae Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 9219 ; free virtual = 43861 Phase 2 Global Placement INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24715 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 8791 ; free virtual = 43433 --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8773 ; free virtual = 43415 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8770 ; free virtual = 43412 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 20d0b931e Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8768 ; free virtual = 43410 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1e6e670e9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8760 ; free virtual = 43402 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b09ad14e Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8754 ; free virtual = 43396 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8726 ; free virtual = 43368 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8726 ; free virtual = 43368 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8725 ; free virtual = 43367 Phase 3 Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8723 ; free virtual = 43365 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8719 ; free virtual = 43361 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8715 ; free virtual = 43358 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8715 ; free virtual = 43357 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8714 ; free virtual = 43356 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8713 ; free virtual = 43355 Ending Placer Task | Checksum: 1c94b2d26 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 8725 ; free virtual = 43367 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 8725 ; free virtual = 43367 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4ab841c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:16] 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 8585 ; free virtual = 43227 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24974 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8575 ; free virtual = 43218 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1545.957 ; gain = 0.000 ; free physical = 8579 ; free virtual = 43222 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1545.957 ; gain = 0.000 ; free physical = 8544 ; free virtual = 43193 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8504 ; free virtual = 43148 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 8503 ; free virtual = 43146 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 8426 ; free virtual = 43069 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 8308 ; free virtual = 42951 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- No constraint files found. Finished Synthesize : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8087 ; free virtual = 42731 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8089 ; free virtual = 42738 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 8080 ; free virtual = 42724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8080 ; free virtual = 42724 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 8080 ; free virtual = 42724 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8025 ; free virtual = 42669 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 7965 ; free virtual = 42609 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7948 ; free virtual = 42592 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: aa30cc8b --------------------------------------------------------------------------------- Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2056.934 ; gain = 120.668 ; free physical = 7944 ; free virtual = 42587 Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7944 ; free virtual = 42587 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: aa30cc8b Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 7908 ; free virtual = 42551 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: aa30cc8b --------------------------------------------------------------------------------- Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 7908 ; free virtual = 42551 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7906 ; free virtual = 42550 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7901 ; free virtual = 42544 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7900 ; free virtual = 42543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7898 ; free virtual = 42542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7898 ; free virtual = 42542 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 7935 ; free virtual = 42579 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 7937 ; free virtual = 42581 INFO: [Project 1-571] Translating synthesized netlist Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2053.934 ; gain = 120.668 ; free physical = 7909 ; free virtual = 42553 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 127.656 ; free physical = 7877 ; free virtual = 42520 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2060.922 ; gain = 127.656 ; free physical = 7877 ; free virtual = 42520 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7869 ; free virtual = 42512 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 7849 ; free virtual = 42492 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7848 ; free virtual = 42491 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7844 ; free virtual = 42488 Phase 4 Rip-up And Reroute | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7844 ; free virtual = 42487 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7844 ; free virtual = 42487 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7844 ; free virtual = 42487 Phase 6 Post Hold Fix | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7844 ; free virtual = 42487 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7841 ; free virtual = 42484 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 7842 ; free virtual = 42485 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.977 ; gain = 134.711 ; free physical = 7841 ; free virtual = 42484 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c45c954e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.977 ; gain = 134.711 ; free physical = 7841 ; free virtual = 42484 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.977 ; gain = 134.711 ; free physical = 7873 ; free virtual = 42517 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2109.766 ; gain = 205.516 ; free physical = 7873 ; free virtual = 42516 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1272] Writing placer database... Writing XDEF routing. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 7866 ; free virtual = 42510 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7866 ; free virtual = 42510 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7866 ; free virtual = 42510 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7866 ; free virtual = 42510 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7866 ; free virtual = 42510 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7866 ; free virtual = 42510 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7866 ; free virtual = 42510 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 7858 ; free virtual = 42501 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 136.711 ; free physical = 7856 ; free virtual = 42500 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 136.711 ; free physical = 7854 ; free virtual = 42498 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.977 ; gain = 136.711 ; free physical = 7885 ; free virtual = 42529 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2108.766 ; gain = 207.516 ; free physical = 7880 ; free virtual = 42523 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 7828 ; free virtual = 42474 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1610a2161 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.934 ; gain = 94.668 ; free physical = 7762 ; free virtual = 42406 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1610a2161 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 99.656 ; free physical = 7692 ; free virtual = 42336 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1610a2161 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 99.656 ; free physical = 7691 ; free virtual = 42335 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7633 ; free virtual = 42277 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7598 ; free virtual = 42242 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7582 ; free virtual = 42226 Phase 4 Rip-up And Reroute | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7582 ; free virtual = 42226 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7581 ; free virtual = 42225 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7577 ; free virtual = 42221 Phase 6 Post Hold Fix | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7576 ; free virtual = 42220 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 106.711 ; free physical = 7494 ; free virtual = 42140 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 109.711 ; free physical = 7491 ; free virtual = 42138 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f655770e Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 109.711 ; free physical = 7487 ; free virtual = 42134 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 109.711 ; free physical = 7519 ; free virtual = 42166 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2110.766 ; gain = 180.516 ; free physical = 7518 ; free virtual = 42166 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 7536 ; free virtual = 42181 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 7413 ; free virtual = 42057 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 7404 ; free virtual = 42049 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7372 ; free virtual = 42016 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7067 ; free virtual = 41711 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7064 ; free virtual = 41708 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7063 ; free virtual = 41707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7061 ; free virtual = 41706 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7062 ; free virtual = 41706 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7060 ; free virtual = 41704 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7058 ; free virtual = 41703 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 7053 ; free virtual = 41697 Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 7053 ; free virtual = 41697 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 6944 ; free virtual = 41588 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 6800 ; free virtual = 41445 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Loading data files... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2004.160 ; gain = 458.203 ; free physical = 6736 ; free virtual = 41381 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2055.930 ; gain = 93.668 ; free physical = 6709 ; free virtual = 41353 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.918 ; gain = 98.656 ; free physical = 6679 ; free virtual = 41323 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dc8ba1ed Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.918 ; gain = 98.656 ; free physical = 6679 ; free virtual = 41323 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 927a5c4b Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.973 ; gain = 104.711 ; free physical = 6686 ; free virtual = 41330 Phase 3 Initial Routing Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Build RT Design | Checksum: 15e82b8af Phase 1 Placer Initialization Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.926 ; gain = 41.668 ; free physical = 6673 ; free virtual = 41317 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 6648 ; free virtual = 41292 Number of Nodes with overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 3 Initial Routing | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 6627 ; free virtual = 41271 Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2066.914 ; gain = 47.656 ; free physical = 6627 ; free virtual = 41271 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2066.914 ; gain = 47.656 ; free physical = 6627 ; free virtual = 41271 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 6620 ; free virtual = 41264 Phase 4 Rip-up And Reroute | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 6620 ; free virtual = 41264 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 6619 ; free virtual = 41264 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 6619 ; free virtual = 41264 Phase 6 Post Hold Fix | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.973 ; gain = 105.711 ; free physical = 6619 ; free virtual = 41264 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1546.949 ; gain = 0.000 ; free physical = 6599 ; free virtual = 41244 Phase 7 Route finalize | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.973 ; gain = 106.711 ; free physical = 6599 ; free virtual = 41243 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.973 ; gain = 108.711 ; free physical = 6597 ; free virtual = 41241 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.973 ; gain = 108.711 ; free physical = 6596 ; free virtual = 41241 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.973 ; gain = 108.711 ; free physical = 6628 ; free virtual = 41272 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2109.762 ; gain = 179.516 ; free physical = 6627 ; free virtual = 41272 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 6580 ; free virtual = 41226 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2077.094 ; gain = 57.836 ; free physical = 6534 ; free virtual = 41179 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6427 ; free virtual = 41071 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6407 ; free virtual = 41051 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6404 ; free virtual = 41048 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6402 ; free virtual = 41046 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6401 ; free virtual = 41045 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6400 ; free virtual = 41045 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.094 ; gain = 59.836 ; free physical = 6369 ; free virtual = 41014 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2081.094 ; gain = 61.836 ; free physical = 6367 ; free virtual = 41012 Phase 9 Depositing Routes INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2081.094 ; gain = 61.836 ; free physical = 6373 ; free virtual = 41018 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2081.094 ; gain = 61.836 ; free physical = 6410 ; free virtual = 41054 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2119.883 ; gain = 132.641 ; free physical = 6411 ; free virtual = 41056 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2119.883 ; gain = 0.000 ; free physical = 6514 ; free virtual = 41162 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.160 ; gain = 458.203 ; free physical = 6429 ; free virtual = 41092 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.160 ; gain = 458.203 ; free physical = 6365 ; free virtual = 41031 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 6446 ; free virtual = 41093 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2004.160 ; gain = 458.203 ; free physical = 6460 ; free virtual = 41107 Phase 2 Global Placement Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.172 ; gain = 42.668 ; free physical = 6491 ; free virtual = 41158 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 6438 ; free virtual = 41104 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 6435 ; free virtual = 41102 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 6317 ; free virtual = 40964 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 6315 ; free virtual = 40962 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2083.465 ; gain = 59.961 ; free physical = 6294 ; free virtual = 40941 Phase 3 Initial Routing INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 6240 ; free virtual = 40887 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 6226 ; free virtual = 40873 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 6225 ; free virtual = 40871 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 6226 ; free virtual = 40873 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 6228 ; free virtual = 40875 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 6226 ; free virtual = 40873 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading site data... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 6241 ; free virtual = 40888 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 6239 ; free virtual = 40886 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 6147 ; free virtual = 40794 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 6181 ; free virtual = 40828 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 6177 ; free virtual = 40824 Loading route data... Processing options... Creating bitmap... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.40 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 6127 ; free virtual = 40777 Loading site data... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading route data... Processing options... Creating bitmap... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.953 ; gain = 40.668 ; free physical = 5949 ; free virtual = 40596 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.941 ; gain = 47.656 ; free physical = 5902 ; free virtual = 40549 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.941 ; gain = 47.656 ; free physical = 5904 ; free virtual = 40552 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 5899 ; free virtual = 40546 Phase 2 Router Initialization | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2087.246 ; gain = 60.961 ; free physical = 5899 ; free virtual = 40546 Phase 3 Initial Routing Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Creating bitstream... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 5817 ; free virtual = 40464 Phase 3.2 Commit Most Macros & LUTRAMs Number of Nodes with overlaps = 0 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3 Initial Routing | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5849 ; free virtual = 40496 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5862 ; free virtual = 40510 Phase 4 Rip-up And Reroute | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5862 ; free virtual = 40509 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5862 ; free virtual = 40509 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5861 ; free virtual = 40508 Phase 6 Post Hold Fix | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5858 ; free virtual = 40506 Loading data files... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 5801 ; free virtual = 40448 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.246 ; gain = 63.961 ; free physical = 5794 ; free virtual = 40441 Phase 9 Depositing Routes Loading data files... Phase 9 Depositing Routes | Checksum: 1aab43f05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 5838 ; free virtual = 40485 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 5873 ; free virtual = 40520 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2130.035 ; gain = 135.766 ; free physical = 5873 ; free virtual = 40520 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 5863 ; free virtual = 40510 Writing placer database... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3.3 Area Swap Optimization INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Writing XDEF routing. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:44 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 5876 ; free virtual = 40526 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 5876 ; free virtual = 40526 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Write XDEF Complete: Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2130.035 ; gain = 0.000 ; free physical = 5875 ; free virtual = 40525 INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 5842 ; free virtual = 40493 Phase 3.5 Small Shape Detail Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Processing options... Creating bitmap... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 5882 ; free virtual = 40534 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 5891 ; free virtual = 40543 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.51 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 5935 ; free virtual = 40587 Writing bitstream ./design.bit... Creating bitstream... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 5977 ; free virtual = 40633 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6163 ; free virtual = 40819 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.7 Pipeline Register Optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6165 ; free virtual = 40821 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6121 ; free virtual = 40777 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Loading data files... Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6060 ; free virtual = 40717 Phase 4.2 Post Placement Cleanup WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6078 ; free virtual = 40734 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6031 ; free virtual = 40687 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6003 ; free virtual = 40659 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6027 ; free virtual = 40683 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2092.203 ; gain = 546.246 ; free physical = 6002 ; free virtual = 40658 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.203 ; gain = 624.949 ; free physical = 5995 ; free virtual = 40651 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 5928 ; free virtual = 40588 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:05 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.871 ; gain = 344.105 ; free physical = 6164 ; free virtual = 40824 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:05 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 6201 ; free virtual = 40861 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Bitstream size: 4243411 bytes Starting Routing Task Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:05 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2451.871 ; gain = 343.105 ; free physical = 7109 ; free virtual = 41769 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:05 2019... Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 7506 ; free virtual = 42166 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Bitstream size: 4243411 bytes Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 7901 ; free virtual = 42561 Phase 2.2 Pre Route Cleanup Config size: 1060815 words Number of configuration frames: 9996 Phase 2.2 Pre Route Cleanup | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 7894 ; free virtual = 42554 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 7879 ; free virtual = 42539 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 12e953610 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7779 ; free virtual = 42439 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7734 ; free virtual = 42394 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7747 ; free virtual = 42407 Phase 4 Rip-up And Reroute | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7748 ; free virtual = 42408 Phase 5 Delay and Skew Optimization Loading site data... Phase 5 Delay and Skew Optimization | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7785 ; free virtual = 42445 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7785 ; free virtual = 42445 Phase 6 Post Hold Fix | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7784 ; free virtual = 42444 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7753 ; free virtual = 42413 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7751 ; free virtual = 42411 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7737 ; free virtual = 42397 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 7768 ; free virtual = 42429 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2139.020 ; gain = 46.473 ; free physical = 7769 ; free virtual = 42429 Loading route data... Processing options... Creating bitmap... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2139.020 ; gain = 0.000 ; free physical = 7743 ; free virtual = 42406 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 7630 ; free virtual = 42290 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:08 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2451.871 ; gain = 341.105 ; free physical = 7607 ; free virtual = 42268 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:08 2019... --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 7627 ; free virtual = 42287 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 7685 ; free virtual = 42346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 7733 ; free virtual = 42393 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 7958 ; free virtual = 42619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Loading route data... --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8285 ; free virtual = 42945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8445 ; free virtual = 43106 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Processing options... Creating bitmap... Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8578 ; free virtual = 43239 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8579 ; free virtual = 43239 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 8124 ; free virtual = 42789 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 8233 ; free virtual = 42902 Phase 1.3 Build Placer Netlist Model Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Creating bitstream... 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2453.867 ; gain = 344.105 ; free physical = 8006 ; free virtual = 42676 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:18 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 8960 ; free virtual = 43629 Phase 1.4 Constrain Clocks/Macros Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 8955 ; free virtual = 43624 touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 456.203 ; free physical = 8947 ; free virtual = 43616 Phase 2 Global Placement WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9066 ; free virtual = 43744 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 8971 ; free virtual = 43649 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9010 ; free virtual = 43687 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 9010 ; free virtual = 43687 Phase 3.3 Area Swap Optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 8977 ; free virtual = 43654 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 3.4 Pipeline Register Optimization 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2460.988 ; gain = 341.105 ; free physical = 8991 ; free virtual = 43669 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:24 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 9030 ; free virtual = 43708 Phase 3.5 Small Shape Detail Placement 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2471.359 ; gain = 343.105 ; free physical = 9057 ; free virtual = 43734 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:24 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2004.156 ; gain = 453.203 ; free physical = 10815 ; free virtual = 45494 Phase 1.3 Build Placer Netlist Model Loading site data... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10643 ; free virtual = 45322 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10731 ; free virtual = 45409 Phase 3.7 Pipeline Register Optimization Loading route data... Processing options... Creating bitmap... Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10767 ; free virtual = 45446 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10704 ; free virtual = 45383 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10741 ; free virtual = 45419 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10732 ; free virtual = 45411 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10713 ; free virtual = 45392 Phase 4.4 Final Placement Cleanup Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10702 ; free virtual = 45382 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10699 ; free virtual = 45381 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 552.250 ; free physical = 10864 ; free virtual = 45547 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 630.953 ; free physical = 10869 ; free virtual = 45552 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2004.156 ; gain = 453.203 ; free physical = 10970 ; free virtual = 45653 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2004.156 ; gain = 453.203 ; free physical = 10966 ; free virtual = 45649 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27172 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2004.156 ; gain = 453.203 ; free physical = 10964 ; free virtual = 45647 Phase 2 Global Placement WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27502 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.141 ; gain = 340.105 ; free physical = 10745 ; free virtual = 45428 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:33 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11708 ; free virtual = 46392 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11692 ; free virtual = 46377 Phase 3.2 Commit Most Macros & LUTRAMs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11622 ; free virtual = 46306 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11604 ; free virtual = 46288 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11652 ; free virtual = 46336 Phase 3.5 Small Shape Detail Placement Writing bitstream ./design.bit... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27993 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11894 ; free virtual = 46583 Phase 3.6 Re-assign LUT pins INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11907 ; free virtual = 46595 Phase 3.7 Pipeline Register Optimization 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 11932 ; free virtual = 46621 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11930 ; free virtual = 46619 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11929 ; free virtual = 46618 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11854 ; free virtual = 46543 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11762 ; free virtual = 46451 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11716 ; free virtual = 46405 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11685 ; free virtual = 46374 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11668 ; free virtual = 46357 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2108.207 ; gain = 557.254 ; free physical = 11781 ; free virtual = 46470 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2108.207 ; gain = 639.957 ; free physical = 11781 ; free virtual = 46470 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11707 ; free virtual = 46396 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:42:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.125 ; gain = 335.105 ; free physical = 11656 ; free virtual = 46345 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:42:39 2019... Phase 1 Placer Initialization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1556.855 ; gain = 0.000 ; free physical = 11736 ; free virtual = 46425 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.76 . Memory (MB): peak = 1556.855 ; gain = 0.000 ; free physical = 12630 ; free virtual = 47318 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 --------------------------------------------------------------------------------- Phase 1 Build RT Design Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 12587 ; free virtual = 47277 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 12559 ; free virtual = 47249 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 12556 ; free virtual = 47245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 12573 ; free virtual = 47263 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 12570 ; free virtual = 47260 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 28103 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 12447 ; free virtual = 47138 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 12443 ; free virtual = 47133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 12445 ; free virtual = 47135 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 12446 ; free virtual = 47136 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 12267 ; free virtual = 46957 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2352] INFO: Launching helper process for spawning children vivado processesWARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Helper process launched with PID 28185 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28186 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11736 ; free virtual = 46426 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11728 ; free virtual = 46418 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11729 ; free virtual = 46419 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.434 ; gain = 38.230 ; free physical = 11655 ; free virtual = 46345 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2136.422 ; gain = 44.219 ; free physical = 11610 ; free virtual = 46300 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2136.422 ; gain = 44.219 ; free physical = 11610 ; free virtual = 46300 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11590 ; free virtual = 46281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11577 ; free virtual = 46268 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11577 ; free virtual = 46267 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11576 ; free virtual = 46266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11575 ; free virtual = 46266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11574 ; free virtual = 46264 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11573 ; free virtual = 46263 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11572 ; free virtual = 46263 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11570 ; free virtual = 46260 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 11571 ; free virtual = 46261 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11515 ; free virtual = 46205 Phase 3 Initial Routing Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11497 ; free virtual = 46187 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11496 ; free virtual = 46186 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11495 ; free virtual = 46186 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11495 ; free virtual = 46186 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11495 ; free virtual = 46185 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11495 ; free virtual = 46185 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.926 ; gain = 207.484 ; free physical = 11488 ; free virtual = 46178 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11487 ; free virtual = 46177 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11486 ; free virtual = 46176 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11483 ; free virtual = 46173 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.477 ; gain = 63.273 ; free physical = 11524 ; free virtual = 46214 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2194.266 ; gain = 102.062 ; free physical = 11523 ; free virtual = 46213 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.926 ; gain = 207.484 ; free physical = 11517 ; free virtual = 46207 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11513 ; free virtual = 46204 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11543 ; free virtual = 46236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11534 ; free virtual = 46228 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11533 ; free virtual = 46227 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11528 ; free virtual = 46223 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11515 ; free virtual = 46213 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11514 ; free virtual = 46212 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11512 ; free virtual = 46210 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11512 ; free virtual = 46210 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11509 ; free virtual = 46207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11509 ; free virtual = 46207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11508 ; free virtual = 46207 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 11508 ; free virtual = 46206 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.910 ; gain = 215.461 ; free physical = 11508 ; free virtual = 46207 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.266 ; gain = 0.000 ; free physical = 11210 ; free virtual = 45923 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 11234 ; free virtual = 45947 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: Launching helper process for spawning children vivado processes INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11285 ; free virtual = 46000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11285 ; free virtual = 46000 INFO: Helper process launched with PID 28302 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 11204 ; free virtual = 45896 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 11200 ; free virtual = 45892 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1401.926 ; gain = 319.039 ; free physical = 10960 ; free virtual = 45652 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] Starting Placer Task WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.957 ; gain = 0.000 ; free physical = 10713 ; free virtual = 45405 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1465.957 ; gain = 0.000 ; free physical = 10713 ; free virtual = 45405 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 10699 ; free virtual = 45391 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 10724 ; free virtual = 45421 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 10723 ; free virtual = 45420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 10722 ; free virtual = 45416 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 10719 ; free virtual = 45412 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 10715 ; free virtual = 45408 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 10716 ; free virtual = 45409 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 10722 ; free virtual = 45415 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 10650 ; free virtual = 45359 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1963.344 ; gain = 0.000 ; free physical = 10647 ; free virtual = 45359 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 10649 ; free virtual = 45361 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10632 ; free virtual = 45345 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10551 ; free virtual = 45245 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10517 ; free virtual = 45230 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10519 ; free virtual = 45232 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10522 ; free virtual = 45235 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10523 ; free virtual = 45237 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10526 ; free virtual = 45240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10529 ; free virtual = 45242 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10532 ; free virtual = 45246 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10535 ; free virtual = 45249 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 10537 ; free virtual = 45251 INFO: [Project 1-571] Translating synthesized netlist INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10461 ; free virtual = 45155 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 10461 ; free virtual = 45156 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2051.387 ; gain = 494.531 ; free physical = 10462 ; free virtual = 45156 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28408 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 10117 ; free virtual = 44811 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9950 ; free virtual = 44644 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3235] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3964] Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2051.387 ; gain = 494.531 ; free physical = 9879 ; free virtual = 44573 Phase 1.4 Constrain Clocks/Macros WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.387 ; gain = 494.531 ; free physical = 9845 ; free virtual = 44539 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 9839 ; free virtual = 44533 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.387 ; gain = 494.531 ; free physical = 9839 ; free virtual = 44533 Phase 2 Final Placement Cleanup WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 9820 ; free virtual = 44515 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 9868 ; free virtual = 44567 --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.387 ; gain = 494.531 ; free physical = 9873 ; free virtual = 44573 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Starting Placer Task --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9872 ; free virtual = 44572 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 9897 ; free virtual = 44592 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 9902 ; free virtual = 44597 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.387 ; gain = 494.531 ; free physical = 9906 ; free virtual = 44610 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9915 ; free virtual = 44610 --------------------------------------------------------------------------------- 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2051.387 ; gain = 574.562 ; free physical = 9916 ; free virtual = 44611 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 9923 ; free virtual = 44618 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9912 ; free virtual = 44607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9912 ; free virtual = 44607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 9928 ; free virtual = 44623 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9921 ; free virtual = 44616 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9846 ; free virtual = 44541 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9841 ; free virtual = 44536 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9839 ; free virtual = 44534 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9837 ; free virtual = 44532 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9836 ; free virtual = 44531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9835 ; free virtual = 44530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9834 ; free virtual = 44529 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9828 ; free virtual = 44523 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 9821 ; free virtual = 44516 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9821 ; free virtual = 44516 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9818 ; free virtual = 44512 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9817 ; free virtual = 44512 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9813 ; free virtual = 44508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9813 ; free virtual = 44508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9814 ; free virtual = 44509 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9814 ; free virtual = 44509 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9814 ; free virtual = 44509 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9813 ; free virtual = 44508 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 9815 ; free virtual = 44510 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement Starting Routing Task INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 9631 ; free virtual = 44325 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2129.957 ; gain = 30.758 ; free physical = 9579 ; free virtual = 44274 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2135.945 ; gain = 36.746 ; free physical = 9524 ; free virtual = 44219 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2135.945 ; gain = 36.746 ; free physical = 9524 ; free virtual = 44219 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 9517 ; free virtual = 44211 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9420 ; free virtual = 44115 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 9419 ; free virtual = 44113 --------------------------------------------------------------------------------- Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9357 ; free virtual = 44052 Loading route data... Processing options... Creating bitmap... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9335 ; free virtual = 44030 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9335 ; free virtual = 44030 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9335 ; free virtual = 44030 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9335 ; free virtual = 44030 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9335 ; free virtual = 44030 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9299 ; free virtual = 43994 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9259 ; free virtual = 43954 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9256 ; free virtual = 43951 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9239 ; free virtual = 43934 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 9267 ; free virtual = 43962 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:45 . Memory (MB): peak = 2193.789 ; gain = 94.590 ; free physical = 9263 ; free virtual = 43958 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 9071 ; free virtual = 43771 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9029 ; free virtual = 43730 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9024 ; free virtual = 43725 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9024 ; free virtual = 43725 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9024 ; free virtual = 43724 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9023 ; free virtual = 43724 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9024 ; free virtual = 43725 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 9024 ; free virtual = 43725 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9017 ; free virtual = 43717 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:867] Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:895] | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Start Renaming Generated Instances --------------------------------------------------------------------------------- Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9005 ; free virtual = 43706 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:16] --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9011 ; free virtual = 43719 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 9012 ; free virtual = 43716 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9011 ; free virtual = 43715 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 9007 ; free virtual = 43711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8990 ; free virtual = 43698 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ --------------------------------------------------------------------------------- +-+--------------+----------+ Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 8992 ; free virtual = 43698 --------------------------------------------------------------------------------- Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8992 ; free virtual = 43697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 8991 ; free virtual = 43696 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8989 ; free virtual = 43694 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 8990 ; free virtual = 43696 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-571] Translating synthesized netlist INFO: [Device 21-403] Loading part xc7z020clg400-1 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 8998 ; free virtual = 43705 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.949 ; gain = 115.504 ; free physical = 8989 ; free virtual = 43696 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully Hierarchical RTL Component report INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors Module top INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : Running DRC as a precondition to command place_design 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 8936 ; free virtual = 43646 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 8818 ; free virtual = 43534 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.789 ; gain = 0.000 ; free physical = 8826 ; free virtual = 43544 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 8826 ; free virtual = 43544 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.715 ; gain = 0.000 ; free physical = 8721 ; free virtual = 43440 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1472.715 ; gain = 0.000 ; free physical = 8736 ; free virtual = 43432 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8764 ; free virtual = 43460 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8593 ; free virtual = 43290 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8559 ; free virtual = 43256 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1814.445 ; gain = 0.000 ; free physical = 8553 ; free virtual = 43254 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 8669 ; free virtual = 43369 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 8668 ; free virtual = 43368 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 8668 ; free virtual = 43368 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 8668 ; free virtual = 43368 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 8668 ; free virtual = 43368 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 8671 ; free virtual = 43371 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1902.488 ; gain = 500.562 ; free physical = 8671 ; free virtual = 43371 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8676 ; free virtual = 43377 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8676 ; free virtual = 43376 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8675 ; free virtual = 43375 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8675 ; free virtual = 43375 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8674 ; free virtual = 43374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8673 ; free virtual = 43374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8673 ; free virtual = 43374 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8673 ; free virtual = 43373 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 8675 ; free virtual = 43376 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2129.430 ; gain = 21.223 ; free physical = 8484 ; free virtual = 43185 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.418 ; gain = 28.211 ; free physical = 8440 ; free virtual = 43140 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.418 ; gain = 28.211 ; free physical = 8440 ; free virtual = 43140 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:43:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.371 ; gain = 338.105 ; free physical = 8343 ; free virtual = 43044 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:43:23 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 8350 ; free virtual = 43050 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9382 ; free virtual = 44082 Bitstream size: 4243411 bytes No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 DONE Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9379 ; free virtual = 44079 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9379 ; free virtual = 44079 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9379 ; free virtual = 44079 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9379 ; free virtual = 44079 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9379 ; free virtual = 44079 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 9361 ; free virtual = 44061 --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9340 ; free virtual = 44040 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9339 ; free virtual = 44039 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9334 ; free virtual = 44034 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.473 ; gain = 47.266 ; free physical = 9369 ; free virtual = 44069 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:45 . Memory (MB): peak = 2194.262 ; gain = 86.055 ; free physical = 9369 ; free virtual = 44069 touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing placer database... Loading data files... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 9380 ; free virtual = 44082 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9372 ; free virtual = 44074 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9167 ; free virtual = 43879 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9165 ; free virtual = 43876 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9162 ; free virtual = 43873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9161 ; free virtual = 43873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9160 ; free virtual = 43871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9159 ; free virtual = 43871 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9159 ; free virtual = 43871 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9155 ; free virtual = 43867 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9156 ; free virtual = 43868 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement Writing XDEF routing. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.262 ; gain = 0.000 ; free physical = 8764 ; free virtual = 43488 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 8805 ; free virtual = 43528 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8749 ; free virtual = 43473 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.746 ; gain = 0.000 ; free physical = 8680 ; free virtual = 43382 Running DRC as a precondition to command write_bitstream Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1481.746 ; gain = 0.000 ; free physical = 8679 ; free virtual = 43381 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8667 ; free virtual = 43369 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8665 ; free virtual = 43367 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8664 ; free virtual = 43366 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8663 ; free virtual = 43365 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8662 ; free virtual = 43364 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8661 ; free virtual = 43362 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8661 ; free virtual = 43362 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 8437 ; free virtual = 43139 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8271 ; free virtual = 42973 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1296e3a58 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8268 ; free virtual = 42970 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading data files... Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.441 ; gain = 0.000 ; free physical = 7684 ; free virtual = 42386 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 7652 ; free virtual = 42354 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 7604 ; free virtual = 42306 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 7562 ; free virtual = 42264 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 7504 ; free virtual = 42206 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 7456 ; free virtual = 42158 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 7412 ; free virtual = 42114 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 583.562 ; free physical = 7409 ; free virtual = 42111 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 7319 ; free virtual = 42021 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 514.531 ; free physical = 7324 ; free virtual = 42026 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 514.531 ; free physical = 7282 ; free virtual = 41984 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 514.531 ; free physical = 7271 ; free virtual = 41973 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 514.531 ; free physical = 7263 ; free virtual = 41965 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 514.531 ; free physical = 7264 ; free virtual = 41966 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.246 ; gain = 514.531 ; free physical = 7266 ; free virtual = 41968 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 7266 ; free virtual = 41968 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 7326 ; free virtual = 42028 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Routing Task Writing bitstream ./design.bit... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1550.859 ; gain = 0.000 ; free physical = 7472 ; free virtual = 42178 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1550.859 ; gain = 0.000 ; free physical = 7467 ; free virtual = 42173 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:43:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2532.895 ; gain = 339.105 ; free physical = 7318 ; free virtual = 42024 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:43:46 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28990 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.234 ; gain = 0.000 ; free physical = 7746 ; free virtual = 42452 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 7663 ; free virtual = 42369 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 7679 ; free virtual = 42385 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 7677 ; free virtual = 42383 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 7675 ; free virtual = 42381 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 7671 ; free virtual = 42378 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.277 ; gain = 511.531 ; free physical = 7653 ; free virtual = 42359 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1993.277 ; gain = 576.562 ; free physical = 7649 ; free virtual = 42355 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2137.070 ; gain = 53.668 ; free physical = 7931 ; free virtual = 42641 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Starting Routing Task Phase 2.1 Fix Topology Constraints INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2.1 Fix Topology Constraints | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2146.059 ; gain = 62.656 ; free physical = 7856 ; free virtual = 42567 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 107963fbc Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2146.059 ; gain = 62.656 ; free physical = 7847 ; free virtual = 42557 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 7662 ; free virtual = 42372 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7658 ; free virtual = 42368 Phase 3 Initial Routing Number of Nodes with overlaps = 0 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 3 Initial Routing | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7652 ; free virtual = 42362 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e1594fd1 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7650 ; free virtual = 42360 Phase 1.3 Build Placer Netlist Model Phase 4.1 Global Iteration 0 | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7650 ; free virtual = 42360 Phase 1.3 Build Placer Netlist Model | Checksum: 278abb5b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7650 ; free virtual = 42360 Phase 1.4 Constrain Clocks/Macros Phase 4 Rip-up And Reroute | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7649 ; free virtual = 42359 Phase 5 Delay and Skew Optimization Phase 1.4 Constrain Clocks/Macros | Checksum: 278abb5b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7648 ; free virtual = 42358 Phase 5 Delay and Skew Optimization | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7648 ; free virtual = 42358 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 1 Placer Initialization | Checksum: 278abb5b7 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 7648 ; free virtual = 42358 Phase 2 Global Placement Phase 6.1 Hold Fix Iter | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7646 ; free virtual = 42356 Phase 6 Post Hold Fix | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7642 ; free virtual = 42352 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7636 ; free virtual = 42346 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7635 ; free virtual = 42345 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c2f462cb Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7614 ; free virtual = 42324 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.363 ; gain = 95.961 ; free physical = 7657 ; free virtual = 42367 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:49 . Memory (MB): peak = 2218.152 ; gain = 166.766 ; free physical = 7657 ; free virtual = 42367 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:43:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2533.367 ; gain = 339.105 ; free physical = 7656 ; free virtual = 42370 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:43:58 2019... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 Phase 2 Global Placement | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8684 ; free virtual = 43407 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8677 ; free virtual = 43400 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 215570181 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8667 ; free virtual = 43391 Phase 3.3 Area Swap Optimization Phase 1 Build RT Design | Checksum: c47cd168 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2056.930 ; gain = 120.668 ; free physical = 8648 ; free virtual = 43373 Phase 3.3 Area Swap Optimization | Checksum: 1ef31df4c Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8645 ; free virtual = 43370 Phase 3.4 Pipeline Register Optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 3.4 Pipeline Register Optimization | Checksum: 1b8e63fb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8641 ; free virtual = 43366 Phase 3.5 Small Shape Detail Placement Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: c47cd168 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2061.918 ; gain = 125.656 ; free physical = 8601 ; free virtual = 43325 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: c47cd168 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2061.918 ; gain = 125.656 ; free physical = 8600 ; free virtual = 43324 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8557 ; free virtual = 43285 Phase 3 Initial Routing Phase 3.5 Small Shape Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8558 ; free virtual = 43286 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8564 ; free virtual = 43293 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8564 ; free virtual = 43293 Phase 3 Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8563 ; free virtual = 43293 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8607 ; free virtual = 43337 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8607 ; free virtual = 43337 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8607 ; free virtual = 43337 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8607 ; free virtual = 43337 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8607 ; free virtual = 43337 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8606 ; free virtual = 43337 Ending Placer Task | Checksum: 146bf3d33 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 8619 ; free virtual = 43350 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 8619 ; free virtual = 43350 Command: route_design Phase 4.1 Global Iteration 0 | Checksum: 1481dbb17 Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8619 ; free virtual = 43350 Phase 4 Rip-up And Reroute | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8619 ; free virtual = 43349 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8619 ; free virtual = 43349 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8619 ; free virtual = 43349 Phase 6 Post Hold Fix | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8619 ; free virtual = 43349 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 8611 ; free virtual = 43343 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 8610 ; free virtual = 43342 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 8610 ; free virtual = 43342 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 8644 ; free virtual = 43376 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2109.762 ; gain = 205.516 ; free physical = 8646 ; free virtual = 43378 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 8640 ; free virtual = 43375 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.152 ; gain = 0.000 ; free physical = 8583 ; free virtual = 43322 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 8529 ; free virtual = 43269 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.152 ; gain = 0.000 ; free physical = 8484 ; free virtual = 43199 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 621f9429 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:923] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 8258 ; free virtual = 42973 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 8233 ; free virtual = 42948 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 8233 ; free virtual = 42947 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 8230 ; free virtual = 42945 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 9c37998b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2054.172 ; gain = 119.668 ; free physical = 7923 ; free virtual = 42637 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9c37998b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2059.160 ; gain = 124.656 ; free physical = 7874 ; free virtual = 42589 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9c37998b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2059.160 ; gain = 124.656 ; free physical = 7874 ; free virtual = 42589 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7903 ; free virtual = 42617 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7826 ; free virtual = 42541 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7827 ; free virtual = 42542 Phase 4 Rip-up And Reroute | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7828 ; free virtual = 42542 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7828 ; free virtual = 42542 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7828 ; free virtual = 42542 Phase 6 Post Hold Fix | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7828 ; free virtual = 42542 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading data files... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2065.215 ; gain = 130.711 ; free physical = 7826 ; free virtual = 42541 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.215 ; gain = 132.711 ; free physical = 7825 ; free virtual = 42539 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12be4f0f0 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.215 ; gain = 132.711 ; free physical = 7825 ; free virtual = 42539 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.215 ; gain = 132.711 ; free physical = 7858 ; free virtual = 42573 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2106.004 ; gain = 203.516 ; free physical = 7858 ; free virtual = 42573 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2106.004 ; gain = 0.000 ; free physical = 7852 ; free virtual = 42568 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 7758 ; free virtual = 42473 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 501.531 ; free physical = 7516 ; free virtual = 42231 Phase 1.3 Build Placer Netlist Model ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29935 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 7335 ; free virtual = 42050 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 7242 ; free virtual = 41957 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7248 ; free virtual = 41963 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7135 ; free virtual = 41850 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7131 ; free virtual = 41846 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7129 ; free virtual = 41844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7127 ; free virtual = 41842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7127 ; free virtual = 41842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7126 ; free virtual = 41841 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7126 ; free virtual = 41841 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 7125 ; free virtual = 41840 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 7125 ; free virtual = 41840 INFO: [Project 1-571] Translating synthesized netlist Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 501.531 ; free physical = 7106 ; free virtual = 41821 Phase 1.4 Constrain Clocks/Macros INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 501.531 ; free physical = 7099 ; free virtual = 41814 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 501.531 ; free physical = 7045 ; free virtual = 41760 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 501.531 ; free physical = 7031 ; free virtual = 41746 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Loading data files... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 501.531 ; free physical = 7049 ; free virtual = 41764 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 7050 ; free virtual = 41765 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 6990 ; free virtual = 41706 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 6948 ; free virtual = 41663 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1016daa37 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 6948 ; free virtual = 41663 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6839 ; free virtual = 41554 Phase 3 Initial Routing Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6810 ; free virtual = 41525 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6806 ; free virtual = 41521 Phase 4 Rip-up And Reroute | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6806 ; free virtual = 41521 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6806 ; free virtual = 41521 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6806 ; free virtual = 41521 Phase 6 Post Hold Fix | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6805 ; free virtual = 41520 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6796 ; free virtual = 41511 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 6794 ; free virtual = 41509 Phase 9 Depositing Routes Loading route data... Phase 9 Depositing Routes | Checksum: aef8114b Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 6792 ; free virtual = 41508 Processing options... Creating bitmap... INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 6821 ; free virtual = 41536 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 6821 ; free virtual = 41536 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 6824 ; free virtual = 41540 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 6573 ; free virtual = 41288 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 6514 ; free virtual = 41234 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e39310c0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 6521 ; free virtual = 41241 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 6715 ; free virtual = 41434 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30048 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:475] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 6542 ; free virtual = 41262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 6539 ; free virtual = 41259 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 6538 ; free virtual = 41258 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.930 ; gain = 43.668 ; free physical = 6531 ; free virtual = 41251 Creating bitstream... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 6474 ; free virtual = 41194 Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.918 ; gain = 50.656 ; free physical = 6474 ; free virtual = 41194 --------------------------------------------------------------------------------- Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2069.918 ; gain = 50.656 ; free physical = 6473 ; free virtual = 41193 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:44:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2452.867 ; gain = 343.105 ; free physical = 6347 ; free virtual = 41067 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2081.098 ; gain = 61.836 ; free physical = 6347 ; free virtual = 41066 Phase 3 Initial Routing INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:44:26 2019... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2066.168 ; gain = 43.668 ; free physical = 6307 ; free virtual = 41027 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6304 ; free virtual = 41023 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.156 ; gain = 50.656 ; free physical = 6286 ; free virtual = 41006 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2073.156 ; gain = 50.656 ; free physical = 6286 ; free virtual = 41006 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6284 ; free virtual = 41004 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6284 ; free virtual = 41003 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6286 ; free virtual = 41006 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6290 ; free virtual = 41010 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6293 ; free virtual = 41012 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading site data... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.098 ; gain = 63.836 ; free physical = 6341 ; free virtual = 41061 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.098 ; gain = 65.836 ; free physical = 6478 ; free virtual = 41198 Phase 9 Depositing Routes Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.098 ; gain = 65.836 ; free physical = 7161 ; free virtual = 41881 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.098 ; gain = 65.836 ; free physical = 7197 ; free virtual = 41917 Routing Is Done. DONE 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2123.887 ; gain = 136.641 ; free physical = 7202 ; free virtual = 41921 Writing placer database... touch build/specimen_003/OK Number of Nodes with overlaps = 0 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2083.461 ; gain = 60.961 ; free physical = 7181 ; free virtual = 41901 Phase 3 Initial Routing Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2123.887 ; gain = 0.000 ; free physical = 7156 ; free virtual = 41878 Loading route data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7096 ; free virtual = 41817 Processing options... Creating bitmap... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7083 ; free virtual = 41803 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7080 ; free virtual = 41800 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7078 ; free virtual = 41798 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7076 ; free virtual = 41796 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7070 ; free virtual = 41791 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 7049 ; free virtual = 41769 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 7035 ; free virtual = 41756 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 7006 ; free virtual = 41726 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 7041 ; free virtual = 41762 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2127.250 ; gain = 136.766 ; free physical = 7041 ; free virtual = 41762 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.62 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2127.250 ; gain = 0.000 ; free physical = 7029 ; free virtual = 41752 Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:44:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2449.109 ; gain = 343.105 ; free physical = 7271 ; free virtual = 41996 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:44:33 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 7911 ; free virtual = 42635 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 7890 ; free virtual = 42615 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 7882 ; free virtual = 42606 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7854 ; free virtual = 42579 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7774 ; free virtual = 42499 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7774 ; free virtual = 42499 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7775 ; free virtual = 42499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7775 ; free virtual = 42499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7775 ; free virtual = 42499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7774 ; free virtual = 42499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7774 ; free virtual = 42499 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 7773 ; free virtual = 42498 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 7777 ; free virtual = 42502 Creating bitstream... INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.961 ; gain = 42.668 ; free physical = 7715 ; free virtual = 42440 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.949 ; gain = 49.656 ; free physical = 7672 ; free virtual = 42397 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.949 ; gain = 49.656 ; free physical = 7668 ; free virtual = 42392 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2087.379 ; gain = 62.086 ; free physical = 7617 ; free virtual = 42342 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7601 ; free virtual = 42326 Creating bitstream... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7599 ; free virtual = 42323 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 4 Rip-up And Reroute | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7598 ; free virtual = 42323 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7597 ; free virtual = 42322 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7597 ; free virtual = 42322 Phase 6 Post Hold Fix | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7597 ; free virtual = 42322 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.379 ; gain = 64.086 ; free physical = 7584 ; free virtual = 42309 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.379 ; gain = 66.086 ; free physical = 7582 ; free virtual = 42307 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1a9a59a62 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.379 ; gain = 67.086 ; free physical = 7564 ; free virtual = 42289 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.379 ; gain = 67.086 ; free physical = 7601 ; free virtual = 42325 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2131.168 ; gain = 137.891 ; free physical = 7600 ; free virtual = 42325 Writing placer database... INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2131.168 ; gain = 0.000 ; free physical = 7605 ; free virtual = 42334 Writing bitstream ./design.bit... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:16] Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8091 ; free virtual = 42826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7983 ; free virtual = 42717 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 7981 ; free virtual = 42716 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 7619 ; free virtual = 42353 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Timing 38-35] Done setting XDC timing constraints. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 7649 ; free virtual = 42383 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:44:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2455.871 ; gain = 344.105 ; free physical = 7615 ; free virtual = 42349 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:44:44 2019... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 190af02d6 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 8486 ; free virtual = 43221 Phase 1.3 Build Placer Netlist Model Bitstream size: 4243411 bytes Config size: 1060815 words Phase 1.3 Build Placer Netlist Model | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 8474 ; free virtual = 43208 Phase 1.4 Constrain Clocks/Macros Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:44:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.4 Constrain Clocks/Macros | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 8453 ; free virtual = 43187 touch build/specimen_004/OK 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:43 . Memory (MB): peak = 2608.312 ; gain = 390.160 ; free physical = 8457 ; free virtual = 43192 Phase 1 Placer Initialization | Checksum: 2280168bc Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 8461 ; free virtual = 43193 Phase 2 Global Placement INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:44:45 2019... GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8503 ; free virtual = 43236 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a69706bf Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 8505 ; free virtual = 43237 Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 9472 ; free virtual = 44205 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE Loading data files... touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 Loading site data... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 9267 ; free virtual = 44001 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 9232 ; free virtual = 43967 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 9232 ; free virtual = 43967 Phase 2 Global Placement | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9179 ; free virtual = 43914 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9165 ; free virtual = 43901 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b3a364ee Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9133 ; free virtual = 43868 Phase 3.3 Area Swap Optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17f6b07bf Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9141 ; free virtual = 43876 Phase 3 Initial Routing Phase 3.3 Area Swap Optimization | Checksum: 18d7e42b9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9133 ; free virtual = 43868 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 15732a31e Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9108 ; free virtual = 43843 Phase 3.5 Small Shape Detail Placement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9108 ; free virtual = 43843 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9101 ; free virtual = 43837 Phase 4 Rip-up And Reroute | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9101 ; free virtual = 43836 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9101 ; free virtual = 43836 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9101 ; free virtual = 43836 Phase 6 Post Hold Fix | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9100 ; free virtual = 43835 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3.5 Small Shape Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9130 ; free virtual = 43865 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9130 ; free virtual = 43865 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9120 ; free virtual = 43855 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 3 Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9120 ; free virtual = 43855 Phase 7 Route finalize | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9119 ; free virtual = 43854 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9109 ; free virtual = 43844 Phase 9 Depositing Routes Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9068 ; free virtual = 43804 Phase 9 Depositing Routes | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9063 ; free virtual = 43798 Phase 4.2 Post Placement Cleanup INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 9101 ; free virtual = 43836 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2141.016 ; gain = 48.473 ; free physical = 9098 ; free virtual = 43834 Phase 4.2 Post Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9096 ; free virtual = 43831 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9090 ; free virtual = 43826 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9087 ; free virtual = 43822 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c9e3899d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9080 ; free virtual = 43815 Ending Placer Task | Checksum: 181b67064 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9087 ; free virtual = 43822 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 9087 ; free virtual = 43822 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 9071 ; free virtual = 43809 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9d16c75a ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9016 ; free virtual = 43751 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8998 ; free virtual = 43734 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8957 ; free virtual = 43693 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31196 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8985 ; free virtual = 43725 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9014 ; free virtual = 43753 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9126 ; free virtual = 43865 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9162 ; free virtual = 43901 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9179 ; free virtual = 43919 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9187 ; free virtual = 43927 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9192 ; free virtual = 43932 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9215 ; free virtual = 43954 INFO: [Vivado 12-1842] Bitgen Completed Successfully. Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9219 ; free virtual = 43958 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading data files... Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Loading route data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:44:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2471.355 ; gain = 344.105 ; free physical = 9172 ; free virtual = 43916 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:44:59 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:44:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2461.992 ; gain = 338.105 ; free physical = 9239 ; free virtual = 43982 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:44:59 2019... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31271 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10593 ; free virtual = 45338 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 10215 ; free virtual = 44960 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 10221 ; free virtual = 44966 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 10225 ; free virtual = 44971 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 10230 ; free virtual = 44975 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 10243 ; free virtual = 44988 --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 10248 ; free virtual = 44994 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Phase 1 Build RT Design | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 10221 ; free virtual = 44966 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 151febe35 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10189 ; free virtual = 44934 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10180 ; free virtual = 44925 Phase 1.4 Constrain Clocks/Macros Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.4 Constrain Clocks/Macros | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10168 ; free virtual = 44913 Phase 1 Placer Initialization | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10155 ; free virtual = 44900 Phase 2 Global Placement Loading route data... Phase 2.1 Fix Topology Constraints Processing options... Creating bitmap... Phase 2.1 Fix Topology Constraints | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 10078 ; free virtual = 44823 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 168520de7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 10061 ; free virtual = 44806 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 9953 ; free virtual = 44702 Phase 3 Initial Routing Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1551.949 ; gain = 0.000 ; free physical = 9998 ; free virtual = 44747 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15eed57fc ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10217 ; free virtual = 44967 # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.80 . Memory (MB): peak = 1551.949 ; gain = 0.000 ; free physical = 10238 ; free virtual = 44987 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10237 ; free virtual = 44986 Phase 4 Rip-up And Reroute | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10229 ; free virtual = 44979 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10229 ; free virtual = 44978 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10229 ; free virtual = 44978 Phase 6 Post Hold Fix | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10230 ; free virtual = 44979 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10214 ; free virtual = 44963 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10211 ; free virtual = 44960 Phase 9 Depositing Routes WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: Launching helper process for spawning children vivado processes Phase 9 Depositing Routes | Checksum: 15eed57fc Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10242 ; free virtual = 44991 INFO: Helper process launched with PID 32087 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2178.492 ; gain = 94.086 ; free physical = 10285 ; free virtual = 45034 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2217.281 ; gain = 164.891 ; free physical = 10285 ; free virtual = 45034 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10273 ; free virtual = 45023 --------------------------------------------------------------------------------- Writing placer database... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10205 ; free virtual = 44960 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10199 ; free virtual = 44954 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 262698c70 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10211 ; free virtual = 44966 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32144 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23c446a3b Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10196 ; free virtual = 44952 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 205f8caa0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10192 ; free virtual = 44948 Phase 3.5 Small Shape Detail Placement INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:45:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.273 ; gain = 339.105 ; free physical = 10160 ; free virtual = 44919 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:45:13 2019... Phase 3.5 Small Shape Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10150 ; free virtual = 44909 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10149 ; free virtual = 44908 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10149 ; free virtual = 44908 Phase 3 Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10153 ; free virtual = 44912 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10164 ; free virtual = 44923 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10207 ; free virtual = 44967 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10210 ; free virtual = 44969 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10210 ; free virtual = 44970 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10224 ; free virtual = 44984 Ending Placer Task | Checksum: 1a3769583 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10256 ; free virtual = 45017 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 10257 ; free virtual = 45018 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11226 ; free virtual = 45990 --------------------------------------------------------------------------------- DONE --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 11217 ; free virtual = 45982 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11214 ; free virtual = 45980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 11213 ; free virtual = 45979 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Creating bitstream... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing XDEF routing. Starting Routing Task Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: bed6ec79 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.281 ; gain = 0.000 ; free physical = 10885 ; free virtual = 45664 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.281 ; gain = 0.000 ; free physical = 10856 ; free virtual = 45610 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 10862 ; free virtual = 45616 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 10843 ; free virtual = 45597 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10852 ; free virtual = 45606 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10905 ; free virtual = 45663 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10908 ; free virtual = 45666 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10920 ; free virtual = 45678 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10923 ; free virtual = 45681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10926 ; free virtual = 45684 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10926 ; free virtual = 45684 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10928 ; free virtual = 45686 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10936 ; free virtual = 45694 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10939 ; free virtual = 45697 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10880 ; free virtual = 45639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 10841 ; free virtual = 45601 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10760 ; free virtual = 45519 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10738 ; free virtual = 45496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:45:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 2474.121 ; gain = 333.105 ; free physical = 10735 ; free virtual = 45494 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:45:22 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10737 ; free virtual = 45496 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 11642 ; free virtual = 46400 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' DONE INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11662 ; free virtual = 46421 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11647 ; free virtual = 46406 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11645 ; free virtual = 46405 --------------------------------------------------------------------------------- touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11652 ; free virtual = 46412 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Starting Placer Task --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11615 ; free virtual = 46375 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11612 ; free virtual = 46371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11609 ; free virtual = 46369 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization --------------------------------------------------------------------------------- Start Renaming Generated Ports Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11609 ; free virtual = 46368 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 11608 ; free virtual = 46368 Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11608 ; free virtual = 46367 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11606 ; free virtual = 46365 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11608 ; free virtual = 46368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11606 ; free virtual = 46366 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11600 ; free virtual = 46359 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11602 ; free virtual = 46362 Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32398 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32429 WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11148 ; free virtual = 45908 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 11182 ; free virtual = 45942 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 11129 ; free virtual = 45889 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 11128 ; free virtual = 45888 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Device 21-403] Loading part xc7z020clg400-1 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 11047 ; free virtual = 45807 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 11046 ; free virtual = 45807 Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 10732 ; free virtual = 45492 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10575 ; free virtual = 45335 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 10579 ; free virtual = 45339 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10572 ; free virtual = 45332 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10569 ; free virtual = 45329 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 451.203 ; free physical = 10559 ; free virtual = 45319 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10540 ; free virtual = 45300 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10540 ; free virtual = 45300 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10538 ; free virtual = 45298 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10536 ; free virtual = 45297 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10535 ; free virtual = 45296 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10535 ; free virtual = 45295 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10533 ; free virtual = 45293 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10522 ; free virtual = 45283 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 10522 ; free virtual = 45283 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10503 ; free virtual = 45264 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 10374 ; free virtual = 45134 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 137afd744 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 10350 ; free virtual = 45110 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137afd744 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 10300 ; free virtual = 45061 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137afd744 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 10298 ; free virtual = 45059 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10322 ; free virtual = 45082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10322 ; free virtual = 45083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10322 ; free virtual = 45083 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10300 ; free virtual = 45060 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11278bc6b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10264 ; free virtual = 45025 Phase 3 Initial Routing Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 451.203 ; free physical = 10264 ; free virtual = 45025 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 451.203 ; free physical = 10231 ; free virtual = 44992 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10224 ; free virtual = 44985 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10215 ; free virtual = 44975 Phase 4 Rip-up And Reroute | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10213 ; free virtual = 44973 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10212 ; free virtual = 44972 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10211 ; free virtual = 44972 Phase 6 Post Hold Fix | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10209 ; free virtual = 44970 Phase 7 Route finalize Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 451.203 ; free physical = 10195 ; free virtual = 44956 Phase 2 Global Placement Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: ceaeb1c8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10171 ; free virtual = 44932 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: ceaeb1c8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10168 ; free virtual = 44929 Phase 9 Depositing Routes INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Phase 9 Depositing Routes | Checksum: ceaeb1c8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10113 ; free virtual = 44874 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] INFO: [Route 35-16] Router Completed Successfully WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 10144 ; free virtual = 44905 Routing Is Done. WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 10140 ; free virtual = 44901 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 10092 ; free virtual = 44860 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10086 ; free virtual = 44850 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10060 ; free virtual = 44822 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10059 ; free virtual = 44821 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10090 ; free virtual = 44852 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1343.559 ; gain = 247.938 ; free physical = 10081 ; free virtual = 44843 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1343.559 ; gain = 247.938 ; free physical = 9950 ; free virtual = 44711 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9947 ; free virtual = 44708 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 557 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9964 ; free virtual = 44726 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 9838 ; free virtual = 44599 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1461.719 ; gain = 0.000 ; free physical = 9837 ; free virtual = 44599 Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9802 ; free virtual = 44563 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9793 ; free virtual = 44555 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading route data... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9784 ; free virtual = 44545 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9781 ; free virtual = 44543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9777 ; free virtual = 44539 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9777 ; free virtual = 44538 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9776 ; free virtual = 44538 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9775 ; free virtual = 44536 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.590 ; gain = 268.961 ; free physical = 9776 ; free virtual = 44537 Processing options... Creating bitmap... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9766 ; free virtual = 44528 INFO: [Project 1-571] Translating synthesized netlist Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9744 ; free virtual = 44505 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9644 ; free virtual = 44406 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9677 ; free virtual = 44439 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9653 ; free virtual = 44415 Phase 3.5 Small Shape Detail Placement INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 9195 ; free virtual = 43956 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9188 ; free virtual = 43949 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9186 ; free virtual = 43948 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9186 ; free virtual = 43948 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9186 ; free virtual = 43948 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9186 ; free virtual = 43948 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 9188 ; free virtual = 43950 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 9188 ; free virtual = 43950 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9167 ; free virtual = 43929 Phase 3.6 Re-assign LUT pins Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9143 ; free virtual = 43905 Phase 3.7 Pipeline Register Optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 9126 ; free virtual = 43888 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 9107 ; free virtual = 43869 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9107 ; free virtual = 43869 --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9087 ; free virtual = 43849 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 9072 ; free virtual = 43834 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 8962 ; free virtual = 43724 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 8908 ; free virtual = 43670 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 8876 ; free virtual = 43638 Phase 4.4 Final Placement Cleanup Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8854 ; free virtual = 43616 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 8849 ; free virtual = 43610 Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8846 ; free virtual = 43608 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8842 ; free virtual = 43604 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8841 ; free virtual = 43603 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8839 ; free virtual = 43601 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8838 ; free virtual = 43600 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8838 ; free virtual = 43599 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 8836 ; free virtual = 43597 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 8836 ; free virtual = 43598 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 8836 ; free virtual = 43597 INFO: [Project 1-571] Translating synthesized netlist Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 547.250 ; free physical = 8826 ; free virtual = 43588 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 630.953 ; free physical = 8825 ; free virtual = 43587 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 8806 ; free virtual = 43568 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1001 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 8788 ; free virtual = 43549 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8765 ; free virtual = 43527 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 8506 ; free virtual = 43267 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 8497 ; free virtual = 43259 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 8512 ; free virtual = 43274 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 8511 ; free virtual = 43273 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 8510 ; free virtual = 43272 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 8510 ; free virtual = 43272 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 8510 ; free virtual = 43272 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 8511 ; free virtual = 43273 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 8511 ; free virtual = 43273 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8490 ; free virtual = 43251 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8488 ; free virtual = 43249 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8485 ; free virtual = 43246 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8484 ; free virtual = 43246 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8484 ; free virtual = 43245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8483 ; free virtual = 43244 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8483 ; free virtual = 43244 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8481 ; free virtual = 43243 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 8480 ; free virtual = 43242 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Creating bitstream... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8298 ; free virtual = 43060 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8268 ; free virtual = 43031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8267 ; free virtual = 43030 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8201 ; free virtual = 42964 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 8184 ; free virtual = 42947 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 8205 ; free virtual = 42968 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1473.957 ; gain = 0.000 ; free physical = 8330 ; free virtual = 43097 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1473.957 ; gain = 0.000 ; free physical = 8335 ; free virtual = 43102 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading site data... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1543.957 ; gain = 0.000 ; free physical = 8301 ; free virtual = 43068 Loading route data... Processing options... Creating bitmap... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.69 . Memory (MB): peak = 1543.957 ; gain = 0.000 ; free physical = 8220 ; free virtual = 42987 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 8260 ; free virtual = 43026 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 8160 ; free virtual = 42926 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 8146 ; free virtual = 42912 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 8134 ; free virtual = 42901 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:45:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:42 . Memory (MB): peak = 2607.441 ; gain = 390.160 ; free physical = 8051 ; free virtual = 42817 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:45:58 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3982] touch build/specimen_003/OK WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4397] GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8653 ; free virtual = 43420 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8654 ; free virtual = 43421 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8657 ; free virtual = 43424 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8641 ; free virtual = 43408 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12358ba72 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8641 ; free virtual = 43408 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8678 ; free virtual = 43458 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8679 ; free virtual = 43451 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8698 ; free virtual = 43470 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8671 ; free virtual = 43444 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8671 ; free virtual = 43443 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: eb842b41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8649 ; free virtual = 43422 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8645 ; free virtual = 43417 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8644 ; free virtual = 43416 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8643 ; free virtual = 43415 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8643 ; free virtual = 43415 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8642 ; free virtual = 43414 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 470.531 ; free physical = 8667 ; free virtual = 43439 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8667 ; free virtual = 43439 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8628 ; free virtual = 43400 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8629 ; free virtual = 43401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8627 ; free virtual = 43399 Phase 4 Rip-up And Reroute | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8627 ; free virtual = 43399 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8626 ; free virtual = 43398 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8624 ; free virtual = 43396 Phase 6 Post Hold Fix | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8625 ; free virtual = 43397 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8610 ; free virtual = 43382 --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8609 ; free virtual = 43382 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8607 ; free virtual = 43379 Phase 9 Depositing Routes Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8606 ; free virtual = 43378 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8604 ; free virtual = 43376 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8603 ; free virtual = 43375 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: f7bb427e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8601 ; free virtual = 43373 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8614 ; free virtual = 43386 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8629 ; free virtual = 43402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ INFO: [Route 35-16] Router Completed Successfully Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8636 ; free virtual = 43408 +------+---------+------+ Routing Is Done. Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2141.016 ; gain = 48.473 ; free physical = 8634 ; free virtual = 43406 Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8636 ; free virtual = 43408 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8635 ; free virtual = 43408 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 8636 ; free virtual = 43408 INFO: [Project 1-571] Translating synthesized netlist Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 8609 ; free virtual = 43384 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:46:10 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 2474.125 ; gain = 334.105 ; free physical = 8432 ; free virtual = 43208 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:46:10 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8471 ; free virtual = 43248 --------------------------------------------------------------------------------- 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 8504 ; free virtual = 43281 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 9389 ; free virtual = 44165 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9365 ; free virtual = 44142 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 9217 ; free virtual = 43995 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 9212 ; free virtual = 43990 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9142 ; free virtual = 43919 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9130 ; free virtual = 43907 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9118 ; free virtual = 43895 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9126 ; free virtual = 43903 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9125 ; free virtual = 43903 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9163 ; free virtual = 43940 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9163 ; free virtual = 43940 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9154 ; free virtual = 43931 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 9153 ; free virtual = 43930 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 8902 ; free virtual = 43679 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 517.531 ; free physical = 8825 ; free virtual = 43602 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 517.531 ; free physical = 8859 ; free virtual = 43637 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 517.531 ; free physical = 8849 ; free virtual = 43627 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 517.531 ; free physical = 8847 ; free virtual = 43625 Phase 2 Final Placement Cleanup INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 517.531 ; free physical = 8844 ; free virtual = 43622 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 517.531 ; free physical = 8832 ; free virtual = 43609 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 8828 ; free virtual = 43605 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 8440 ; free virtual = 43217 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 8010 ; free virtual = 42788 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 459.203 ; free physical = 8001 ; free virtual = 42778 Phase 1.3 Build Placer Netlist Model Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 7977 ; free virtual = 42755 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 7972 ; free virtual = 42749 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 7970 ; free virtual = 42747 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 7969 ; free virtual = 42746 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 7965 ; free virtual = 42742 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Loading route data... Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 7963 ; free virtual = 42741 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 7963 ; free virtual = 42741 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Processing options... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitmap... Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 7941 ; free virtual = 42718 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7865 ; free virtual = 42643 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7865 ; free virtual = 42642 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.160 ; gain = 459.203 ; free physical = 7837 ; free virtual = 42614 Phase 1.4 Constrain Clocks/Macros ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.160 ; gain = 459.203 ; free physical = 7806 ; free virtual = 42583 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.160 ; gain = 459.203 ; free physical = 7769 ; free virtual = 42547 Phase 2 Global Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2171 Creating bitstream... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7617 ; free virtual = 42395 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7615 ; free virtual = 42392 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7588 ; free virtual = 42366 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7551 ; free virtual = 42328 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7516 ; free virtual = 42294 Phase 3.5 Small Shape Detail Placement Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 109653c4d Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2053.930 ; gain = 117.668 ; free physical = 7800 ; free virtual = 42581 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 109653c4d Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 7760 ; free virtual = 42541 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 109653c4d Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 7760 ; free virtual = 42541 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 116fd9d52 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7722 ; free virtual = 42504 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7682 ; free virtual = 42464 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7683 ; free virtual = 42465 Phase 3.6 Re-assign LUT pins Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7682 ; free virtual = 42464 Phase 4 Rip-up And Reroute | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7682 ; free virtual = 42464 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7682 ; free virtual = 42464 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7682 ; free virtual = 42464 Phase 6 Post Hold Fix | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7682 ; free virtual = 42464 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 7672 ; free virtual = 42453 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 7670 ; free virtual = 42451 Phase 9 Depositing Routes Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7670 ; free virtual = 42451 Phase 3.7 Pipeline Register Optimization Phase 9 Depositing Routes | Checksum: 116fd9d52 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 7669 ; free virtual = 42451 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 7702 ; free virtual = 42483 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2109.762 ; gain = 205.516 ; free physical = 7701 ; free virtual = 42482 Writing placer database... Writing XDEF routing. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7689 ; free virtual = 42472 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 7689 ; free virtual = 42472 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7678 ; free virtual = 42460 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7629 ; free virtual = 42411 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7583 ; free virtual = 42365 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7541 ; free virtual = 42323 Phase 4.4 Final Placement Cleanup Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7454 ; free virtual = 42236 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7423 ; free virtual = 42205 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.207 ; gain = 555.250 ; free physical = 7450 ; free virtual = 42232 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.207 ; gain = 631.953 ; free physical = 7449 ; free virtual = 42231 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design INFO: [Timing 38-35] Done setting XDC timing constraints. Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 7447 ; free virtual = 42229 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 7374 ; free virtual = 42155 Phase 1.3 Build Placer Netlist Model ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 7370 ; free virtual = 42152 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 7366 ; free virtual = 42147 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 7361 ; free virtual = 42143 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 7364 ; free virtual = 42146 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 7371 ; free virtual = 42153 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 7372 ; free virtual = 42154 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:46:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.121 ; gain = 334.105 ; free physical = 7390 ; free virtual = 42172 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:46:35 2019... Bitstream size: 4243411 bytes Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2055.934 ; gain = 122.668 ; free physical = 8356 ; free virtual = 43138 Config size: 1060815 words Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Number of configuration frames: 9996 DONE Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.922 ; gain = 127.656 ; free physical = 8320 ; free virtual = 43102 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.922 ; gain = 127.656 ; free physical = 8319 ; free virtual = 43102 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8320 ; free virtual = 43102 Phase 3 Initial Routing Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2129.098 ; gain = 29.898 ; free physical = 8306 ; free virtual = 43088 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.086 ; gain = 36.887 ; free physical = 8207 ; free virtual = 42989 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.086 ; gain = 36.887 ; free physical = 8204 ; free virtual = 42986 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8153 ; free virtual = 42935 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8141 ; free virtual = 42924 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8141 ; free virtual = 42924 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8141 ; free virtual = 42923 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8141 ; free virtual = 42923 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.977 ; gain = 133.711 ; free physical = 8141 ; free virtual = 42923 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: Launching helper process for spawning children vivado processes Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: Helper process launched with PID 2401 Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 8101 ; free virtual = 42883 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 136.711 ; free physical = 8098 ; free virtual = 42880 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 136.711 ; free physical = 8096 ; free virtual = 42879 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2069.977 ; gain = 136.711 ; free physical = 8125 ; free virtual = 42908 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2108.766 ; gain = 207.516 ; free physical = 8122 ; free virtual = 42905 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Number of Nodes with overlaps = 0 Phase 1 Build RT Design Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8115 ; free virtual = 42898 Phase 3 Initial Routing Writing placer database... Writing XDEF routing. --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 8103 ; free virtual = 42887 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 8109 ; free virtual = 42892 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8131 ; free virtual = 42914 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8128 ; free virtual = 42911 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8128 ; free virtual = 42910 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8127 ; free virtual = 42910 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8127 ; free virtual = 42910 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8127 ; free virtual = 42909 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8053 ; free virtual = 42836 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8051 ; free virtual = 42834 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8043 ; free virtual = 42826 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.141 ; gain = 55.941 ; free physical = 8097 ; free virtual = 42880 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:51 . Memory (MB): peak = 2193.930 ; gain = 94.730 ; free physical = 8095 ; free virtual = 42877 Writing placer database... Running DRC as a precondition to command write_bitstream Loading data files... Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.930 ; gain = 0.000 ; free physical = 7817 ; free virtual = 42623 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 7508 ; free virtual = 42292 Running DRC as a precondition to command write_bitstream Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7478 ; free virtual = 42262 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7460 ; free virtual = 42244 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7456 ; free virtual = 42240 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7447 ; free virtual = 42231 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7438 ; free virtual = 42223 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7396 ; free virtual = 42180 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 7395 ; free virtual = 42179 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 7171 ; free virtual = 41955 --------------------------------------------------------------------------------- Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 6929 ; free virtual = 41714 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 6895 ; free virtual = 41679 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 6892 ; free virtual = 41676 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 6886 ; free virtual = 41671 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 6870 ; free virtual = 41655 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 6871 ; free virtual = 41655 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 6871 ; free virtual = 41656 Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6836 ; free virtual = 41621 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6756 ; free virtual = 41540 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6751 ; free virtual = 41536 Phase 4 Rip-up And Reroute | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6751 ; free virtual = 41536 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6751 ; free virtual = 41536 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6751 ; free virtual = 41535 Phase 6 Post Hold Fix | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6751 ; free virtual = 41536 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15dc3536d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6755 ; free virtual = 41540 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15dc3536d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6754 ; free virtual = 41539 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15dc3536d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6755 ; free virtual = 41539 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6790 ; free virtual = 41574 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 6790 ; free virtual = 41574 Loading data files... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 6770 ; free virtual = 41556 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] Creating bitstream... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 6534 ; free virtual = 41324 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 6494 ; free virtual = 41288 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 6492 ; free virtual = 41287 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 6532 ; free virtual = 41326 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 6600 ; free virtual = 41394 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 6646 ; free virtual = 41441 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:46:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2451.867 ; gain = 342.105 ; free physical = 6747 ; free virtual = 41542 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:46:58 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7662 ; free virtual = 42456 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7661 ; free virtual = 42456 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7660 ; free virtual = 42455 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7660 ; free virtual = 42455 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7660 ; free virtual = 42454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7660 ; free virtual = 42454 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7659 ; free virtual = 42454 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 7658 ; free virtual = 42453 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 7658 ; free virtual = 42453 touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") INFO: [Project 1-571] Translating synthesized netlist Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 30 #of tags: 3 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 7500 ; free virtual = 42294 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7460 ; free virtual = 42254 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 7459 ; free virtual = 42253 Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2083.465 ; gain = 59.961 ; free physical = 7399 ; free virtual = 42193 Phase 3 Initial Routing Loading route data... Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2706 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7373 ; free virtual = 42168 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7369 ; free virtual = 42163 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7361 ; free virtual = 42155 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7359 ; free virtual = 42154 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7359 ; free virtual = 42154 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7360 ; free virtual = 42154 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 7353 ; free virtual = 42148 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 7353 ; free virtual = 42147 Phase 9 Depositing Routes INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 7358 ; free virtual = 42153 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 2450.832 ; gain = 342.066 ; free physical = 7378 ; free virtual = 42172 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:02 2019... INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 7398 ; free virtual = 42192 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 7400 ; free virtual = 42194 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 8342 ; free virtual = 43140 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 39 #of tags: 2 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 1353.066 ; gain = 257.152 ; free physical = 8200 ; free virtual = 42995 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.926 ; gain = 43.668 ; free physical = 8193 ; free virtual = 42988 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.914 ; gain = 48.656 ; free physical = 8169 ; free virtual = 42964 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2066.914 ; gain = 48.656 ; free physical = 8176 ; free virtual = 42971 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 8185 ; free virtual = 42980 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2076.969 ; gain = 58.711 ; free physical = 8155 ; free virtual = 42950 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8146 ; free virtual = 42942 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8150 ; free virtual = 42945 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8150 ; free virtual = 42945 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8149 ; free virtual = 42944 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8148 ; free virtual = 42943 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8147 ; free virtual = 42942 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 8115 ; free virtual = 42914 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8114 ; free virtual = 42913 Phase 9 Depositing Routes Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8106 ; free virtual = 42901 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 8139 ; free virtual = 42935 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2119.758 ; gain = 133.516 ; free physical = 8137 ; free virtual = 42933 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 8125 ; free virtual = 42920 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 8126 ; free virtual = 42921 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2119.758 ; gain = 0.000 ; free physical = 8128 ; free virtual = 42925 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.098 ; gain = 265.184 ; free physical = 7948 ; free virtual = 42743 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.098 ; gain = 265.184 ; free physical = 7987 ; free virtual = 42783 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 8210 ; free virtual = 43009 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 8095 ; free virtual = 42895 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 8079 ; free virtual = 42878 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 8021 ; free virtual = 42821 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 7995 ; free virtual = 42795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 7981 ; free virtual = 42781 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 7983 ; free virtual = 42782 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 7986 ; free virtual = 42785 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.074 ; gain = 273.160 ; free physical = 7995 ; free virtual = 42795 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1369.082 ; gain = 273.160 ; free physical = 7998 ; free virtual = 42798 INFO: [Project 1-571] Translating synthesized netlist INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 8000 ; free virtual = 42800 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2532.035 ; gain = 338.105 ; free physical = 7941 ; free virtual = 42744 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:13 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 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256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:251] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:16] INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 9142 ; free virtual = 43946 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 9139 ; free virtual = 43943 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 9139 ; free virtual = 43943 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 9169 ; free virtual = 43974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 8970 ; free virtual = 43775 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:17 2019... INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1 Build RT Design | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 9573 ; free virtual = 44378 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2128.965 ; gain = 29.758 ; free physical = 9573 ; free virtual = 44378 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 9530 ; free virtual = 44335 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1090b26a2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 9528 ; free virtual = 44333 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.953 ; gain = 35.746 ; free physical = 9502 ; free virtual = 44307 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.953 ; gain = 35.746 ; free physical = 9502 ; free virtual = 44307 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9388 ; free virtual = 44193 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2087.375 ; gain = 61.086 ; free physical = 9382 ; free virtual = 44187 Phase 3 Initial Routing Loading route data... Number of Nodes with overlaps = 0 Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9355 ; free virtual = 44160 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 INFO: Launching helper process for spawning children vivado processes Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9361 ; free virtual = 44166 Phase 4.1 Global Iteration 0 | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9361 ; free virtual = 44166 Phase 4 Rip-up And Reroute | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9360 ; free virtual = 44165 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9360 ; free virtual = 44165 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9361 ; free virtual = 44166 Phase 6 Post Hold Fix | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9361 ; free virtual = 44166 INFO: Helper process launched with PID 3028 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9354 ; free virtual = 44159 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9354 ; free virtual = 44159 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9354 ; free virtual = 44159 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9354 ; free virtual = 44159 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9354 ; free virtual = 44159 Creating bitstream... Phase 7 Route finalize Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 9347 ; free virtual = 44152 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 9353 ; free virtual = 44158 Phase 9 Depositing Routes Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9340 ; free virtual = 44145 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9339 ; free virtual = 44144 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9337 ; free virtual = 44142 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2155.008 ; gain = 55.801 ; free physical = 9371 ; free virtual = 44176 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2193.797 ; gain = 94.590 ; free physical = 9371 ; free virtual = 44176 Phase 9 Depositing Routes | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 9357 ; free virtual = 44164 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 9392 ; free virtual = 44199 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2130.164 ; gain = 135.891 ; free physical = 9388 ; free virtual = 44198 Writing placer database... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 9337 ; free virtual = 44148 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9307 ; free virtual = 44120 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9273 ; free virtual = 44085 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9219 ; free virtual = 44031 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9170 ; free virtual = 43990 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9163 ; free virtual = 43983 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9162 ; free virtual = 43982 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9162 ; free virtual = 43982 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9160 ; free virtual = 43980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9160 ; free virtual = 43980 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9185 ; free virtual = 44005 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9183 ; free virtual = 44004 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 9182 ; free virtual = 44004 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 9230 ; free virtual = 44060 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.797 ; gain = 0.000 ; free physical = 9187 ; free virtual = 44020 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3142 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.797 ; gain = 0.000 ; free physical = 9178 ; free virtual = 43989 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9108 ; free virtual = 43919 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9099 ; free virtual = 43910 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9098 ; free virtual = 43909 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9098 ; free virtual = 43909 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9098 ; free virtual = 43909 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 9099 ; free virtual = 43910 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 9099 ; free virtual = 43910 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Loading data files... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:29 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2471.359 ; gain = 343.105 ; free physical = 8992 ; free virtual = 43803 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:29 2019... Phase 1 Build RT Design | Checksum: 1370b43a3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 9061 ; free virtual = 43872 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1370b43a3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.945 ; gain = 48.656 ; free physical = 9432 ; free virtual = 44243 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1370b43a3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.945 ; gain = 48.656 ; free physical = 9541 ; free virtual = 44352 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 9838 ; free virtual = 44649 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9756 ; free virtual = 44567 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9727 ; free virtual = 44538 Phase 4 Rip-up And Reroute | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9723 ; free virtual = 44534 Phase 5 Delay and Skew Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 5 Delay and Skew Optimization | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9712 ; free virtual = 44523 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 6.1 Hold Fix Iter | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9709 ; free virtual = 44520 Phase 6 Post Hold Fix | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9702 ; free virtual = 44513 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 9729 ; free virtual = 44540 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 7 Route finalize | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 9718 ; free virtual = 44529 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 157ee683c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 9713 ; free virtual = 44525 Phase 9 Depositing Routes Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 157ee683c Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 9791 ; free virtual = 44603 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 9826 ; free virtual = 44638 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.039 ; gain = 136.766 ; free physical = 9824 ; free virtual = 44636 Writing bitstream ./design.bit... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 9850 ; free virtual = 44668 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9951 ; free virtual = 44768 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1585d46d4 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 9955 ; free virtual = 44771 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 10000 ; free virtual = 44817 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 9824 ; free virtual = 44641 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:139] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 report_drc (run_mandatory_drcs) completed successfully Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Running DRC as a precondition to command place_design Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:35 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 2459.863 ; gain = 340.105 ; free physical = 9749 ; free virtual = 44565 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:35 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 9774 ; free virtual = 44594 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 9834 ; free virtual = 44650 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10663 ; free virtual = 45479 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10669 ; free virtual = 45485 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:15 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 10623 ; free virtual = 45440 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3369 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1563.855 ; gain = 0.000 ; free physical = 10326 ; free virtual = 45143 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:83] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:16] Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.74 . Memory (MB): peak = 1563.855 ; gain = 0.000 ; free physical = 10336 ; free virtual = 45153 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10346 ; free virtual = 45163 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10310 ; free virtual = 45128 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10310 ; free virtual = 45127 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 10285 ; free virtual = 45103 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3458 Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9389 ; free virtual = 44207 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9441 ; free virtual = 44258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9428 ; free virtual = 44245 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9420 ; free virtual = 44239 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9380 ; free virtual = 44198 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 9364 ; free virtual = 44182 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9361 ; free virtual = 44179 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9355 ; free virtual = 44172 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9354 ; free virtual = 44172 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9345 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9345 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9345 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9345 ; free virtual = 44163 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9345 ; free virtual = 44162 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9344 ; free virtual = 44162 Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 9345 ; free virtual = 44163 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9288 ; free virtual = 44106 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9287 ; free virtual = 44105 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] Report RTL Partitions: +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] --------------------------------------------------------------------------------- INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9286 ; free virtual = 44103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9285 ; free virtual = 44103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9284 ; free virtual = 44101 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9282 ; free virtual = 44100 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 9279 ; free virtual = 44097 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 9279 ; free virtual = 44096 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1909.457 ; gain = 0.000 ; free physical = 9048 ; free virtual = 43874 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:16] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d38ee6f1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 9141 ; free virtual = 43967 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 9126 ; free virtual = 43952 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 9119 ; free virtual = 43945 Phase 1 Placer Initialization | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1997.500 ; gain = 508.531 ; free physical = 9114 ; free virtual = 43940 Phase 2 Global Placement WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 9144 ; free virtual = 43972 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9126 ; free virtual = 43952 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 9210 ; free virtual = 44036 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9163 ; free virtual = 43990 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9161 ; free virtual = 43987 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2531.902 ; gain = 338.105 ; free physical = 9140 ; free virtual = 43967 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:55 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 9232 ; free virtual = 44059 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: Helper process launched with PID 4018 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] Starting Placer Task WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] touch build/specimen_006/OK WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] Phase 1 Placer Initialization WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] Phase 1.1 Placer Initialization Netlist Sorting WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10132 ; free virtual = 44958 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15fdaa0f7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10122 ; free virtual = 44949 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10097 ; free virtual = 44923 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10101 ; free virtual = 44928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10100 ; free virtual = 44927 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10100 ; free virtual = 44927 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16bd26d57 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10093 ; free virtual = 44920 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10092 ; free virtual = 44919 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:47:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2470.270 ; gain = 340.105 ; free physical = 10094 ; free virtual = 44921 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:47:57 2019... Phase 2 Global Placement | Checksum: 262ca559a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10302 ; free virtual = 45129 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 262ca559a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 11017 ; free virtual = 45844 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23e660b1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 11065 ; free virtual = 45892 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21840e8ea Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 11040 ; free virtual = 45868 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e1f5494f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 11035 ; free virtual = 45863 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 10862 ; free virtual = 45690 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Phase 3.5 Small Shape Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10827 ; free virtual = 45656 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10818 ; free virtual = 45647 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10809 ; free virtual = 45638 touch build/specimen_005/OK Phase 3 Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10804 ; free virtual = 45632 GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10782 ; free virtual = 45611 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10794 ; free virtual = 45623 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10793 ; free virtual = 45621 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10791 ; free virtual = 45619 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10781 ; free virtual = 45610 Ending Placer Task | Checksum: 1cc0c8886 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2085.543 ; gain = 596.574 ; free physical = 10784 ; free virtual = 45612 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2085.543 ; gain = 660.605 ; free physical = 10781 ; free virtual = 45609 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } INFO: [Timing 38-35] Done setting XDC timing constraints. # run INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 10662 ; free virtual = 45491 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e76cdf7c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4443 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.387 ; gain = 488.531 ; free physical = 10826 ; free virtual = 45659 Phase 1.3 Build Placer Netlist Model Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 10771 ; free virtual = 45604 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 10761 ; free virtual = 45594 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10731 ; free virtual = 45564 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 10685 ; free virtual = 45517 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 10676 ; free virtual = 45509 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 10674 ; free virtual = 45506 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10671 ; free virtual = 45504 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10671 ; free virtual = 45503 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10668 ; free virtual = 45500 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10668 ; free virtual = 45500 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10667 ; free virtual = 45500 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10666 ; free virtual = 45499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10664 ; free virtual = 45497 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10665 ; free virtual = 45498 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 10667 ; free virtual = 45500 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:48:05 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.145 ; gain = 340.105 ; free physical = 10668 ; free virtual = 45500 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:48:05 2019... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 11287 ; free virtual = 46119 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11635 ; free virtual = 46468 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11634 ; free virtual = 46467 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11633 ; free virtual = 46466 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11631 ; free virtual = 46464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11631 ; free virtual = 46464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11631 ; free virtual = 46464 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11631 ; free virtual = 46464 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 11630 ; free virtual = 46463 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 11632 ; free virtual = 46465 INFO: [Project 1-571] Translating synthesized netlist touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 488.531 ; free physical = 11592 ; free virtual = 46426 Phase 1.4 Constrain Clocks/Macros INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 488.531 ; free physical = 11472 ; free virtual = 46306 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.387 ; gain = 488.531 ; free physical = 11441 ; free virtual = 46275 Phase 2 Final Placement Cleanup INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] Phase 2 Final Placement Cleanup | Checksum: 208e4f915 WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 488.531 ; free physical = 11409 ; free virtual = 46244 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 488.531 ; free physical = 11497 ; free virtual = 46332 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11496 ; free virtual = 46331 --------------------------------------------------------------------------------- 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 11497 ; free virtual = 46332 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 11484 ; free virtual = 46319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11484 ; free virtual = 46319 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 11468 ; free virtual = 46303 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f351153a Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2057.930 ; gain = 93.668 ; free physical = 11283 ; free virtual = 46117 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f351153a Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 11202 ; free virtual = 46037 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f351153a Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 11197 ; free virtual = 46031 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11161 ; free virtual = 45995 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 11232 ; free virtual = 46066 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11248 ; free virtual = 46082 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11245 ; free virtual = 46079 Phase 4 Rip-up And Reroute | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11245 ; free virtual = 46079 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11245 ; free virtual = 46079 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11245 ; free virtual = 46079 Phase 6 Post Hold Fix | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11245 ; free virtual = 46079 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f675539e Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 11237 ; free virtual = 46071 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f675539e Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 11235 ; free virtual = 46069 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f675539e Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 11234 ; free virtual = 46069 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.973 ; gain = 108.711 ; free physical = 11265 ; free virtual = 46099 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. report_drc (run_mandatory_drcs) completed successfully route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2111.762 ; gain = 179.516 ; free physical = 11264 ; free virtual = 46099 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2111.762 ; gain = 0.000 ; free physical = 11248 ; free virtual = 46084 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10997 ; free virtual = 45832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 10949 ; free virtual = 45784 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10946 ; free virtual = 45781 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 10957 ; free virtual = 45792 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 10967 ; free virtual = 45802 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 10782 ; free virtual = 45617 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 10773 ; free virtual = 45609 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 10235 ; free virtual = 45070 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 10139 ; free virtual = 44974 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading data files... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1487277ac --------------------------------------------------------------------------------- Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10139 ; free virtual = 44974 Phase 1.3 Build Placer Netlist Model Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10139 ; free virtual = 44974 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10137 ; free virtual = 44972 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10136 ; free virtual = 44971 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10134 ; free virtual = 44970 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 10134 ; free virtual = 44969 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10122 ; free virtual = 44958 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dac8b64b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10107 ; free virtual = 44942 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10096 ; free virtual = 44931 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10094 ; free virtual = 44929 Phase 1 Placer Initialization | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10091 ; free virtual = 44926 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.254 ; gain = 384.367 ; free physical = 10091 ; free virtual = 44927 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10012 ; free virtual = 44847 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 10004 ; free virtual = 44840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9990 ; free virtual = 44825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9987 ; free virtual = 44822 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9986 ; free virtual = 44821 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9983 ; free virtual = 44818 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9982 ; free virtual = 44817 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 9973 ; free virtual = 44808 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 9974 ; free virtual = 44809 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5670 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.957 ; gain = 0.000 ; free physical = 9815 ; free virtual = 44651 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.61 . Memory (MB): peak = 1549.957 ; gain = 0.000 ; free physical = 9782 ; free virtual = 44617 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 2 Global Placement | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9718 ; free virtual = 44554 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d7ade655 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9715 ; free virtual = 44550 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24340a58a Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9711 ; free virtual = 44546 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d1b8355 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9691 ; free virtual = 44526 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6cfe3ba Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9689 ; free virtual = 44524 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9655 ; free virtual = 44490 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9647 ; free virtual = 44483 Phase 3.7 Pipeline Register Optimization Phase 2 Global Placement | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9646 ; free virtual = 44481 Phase 3.7 Pipeline Register Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9646 ; free virtual = 44481 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3 Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9634 ; free virtual = 44469 Phase 3.1 Commit Multi Column Macros | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9616 ; free virtual = 44451 Phase 3.2 Commit Most Macros & LUTRAMs Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9592 ; free virtual = 44429 Phase 4.2 Post Placement Cleanup Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22a14ef89 Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9587 ; free virtual = 44425 Phase 4.2 Post Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9584 ; free virtual = 44423 Phase 4.3 Placer Reporting Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9583 ; free virtual = 44418 Phase 4.4 Final Placement Cleanup Phase 3.3 Area Swap Optimization Phase 4.4 Final Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9620 ; free virtual = 44455 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1abeaee1f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9612 ; free virtual = 44447 Ending Placer Task | Checksum: 163bdd4e6 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9620 ; free virtual = 44455 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 9619 ; free virtual = 44455 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization | Checksum: 203efcd54 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9618 ; free virtual = 44454 Phase 3.4 Pipeline Register Optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.4 Pipeline Register Optimization | Checksum: 1cda42db9 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9575 ; free virtual = 44410 Phase 3.5 Small Shape Detail Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9523 ; free virtual = 44359 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9537 ; free virtual = 44373 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9538 ; free virtual = 44373 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9537 ; free virtual = 44373 Phase 3.7 Pipeline Register Optimization INFO: Launching helper process for spawning children vivado processes--------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9534 ; free virtual = 44369 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9534 ; free virtual = 44370 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Helper process launched with PID 6188 Phase 3 Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9533 ; free virtual = 44368 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9531 ; free virtual = 44366 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9484 ; free virtual = 44320 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9475 ; free virtual = 44311 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9465 ; free virtual = 44301 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9454 ; free virtual = 44290 Ending Placer Task | Checksum: 1c8c94742 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9456 ; free virtual = 44291 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 9454 ; free virtual = 44290 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9406 ; free virtual = 44241 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9395 ; free virtual = 44230 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9392 ; free virtual = 44227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9392 ; free virtual = 44227 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9390 ; free virtual = 44225 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully --------------------------------------------------------------------------------- INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9391 ; free virtual = 44226 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9388 ; free virtual = 44224 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Starting Routing Task Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9389 ; free virtual = 44224 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 9391 ; free virtual = 44226 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 7f1e2bdc ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 9368 ; free virtual = 44204 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4299e38 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 9233 ; free virtual = 44068 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 9226 ; free virtual = 44061 INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 9056 ; free virtual = 43891 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 8935 ; free virtual = 43770 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2073] Command: report_drc (run_mandatory_drcs) for: placer_checks WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2221] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8827 ; free virtual = 43665 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 8831 ; free virtual = 43670 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 8830 ; free virtual = 43669 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 8851 ; free virtual = 43691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8852 ; free virtual = 43692 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Helper process launched with PID 6299 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.434 ; gain = 54.992 ; free physical = 9085 ; free virtual = 43925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9074 ; free virtual = 43914 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:55] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 8604 ; free virtual = 43444 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 8605 ; free virtual = 43446 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.941 ; gain = 99.500 ; free physical = 8558 ; free virtual = 43399 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.969 ; gain = 107.527 ; free physical = 8558 ; free virtual = 43399 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 8571 ; free virtual = 43412 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 8558 ; free virtual = 43399 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.949 ; gain = 115.508 ; free physical = 8558 ; free virtual = 43399 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 8559 ; free virtual = 43400 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 8556 ; free virtual = 43396 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 8553 ; free virtual = 43393 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 8549 ; free virtual = 43390 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 8549 ; free virtual = 43390 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:48:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.867 ; gain = 342.105 ; free physical = 8378 ; free virtual = 43218 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:48:36 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 9066 ; free virtual = 43906 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 8970 ; free virtual = 43810 Phase 1.3 Build Placer Netlist Model Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8944 ; free virtual = 43784 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 8931 ; free virtual = 43772 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8927 ; free virtual = 43767 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 8902 ; free virtual = 43742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8851 ; free virtual = 43692 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8848 ; free virtual = 43688 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8843 ; free virtual = 43683 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8842 ; free virtual = 43682 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8840 ; free virtual = 43680 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8837 ; free virtual = 43677 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8836 ; free virtual = 43677 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8831 ; free virtual = 43671 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 8831 ; free virtual = 43671 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15ca2bf97 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.543 ; gain = 0.000 ; free physical = 8737 ; free virtual = 43577 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 8730 ; free virtual = 43570 Phase 1.4 Constrain Clocks/Macros Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 8745 ; free virtual = 43586 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15ca2bf97 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.543 ; gain = 0.000 ; free physical = 8733 ; free virtual = 43578 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15ca2bf97 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.543 ; gain = 0.000 ; free physical = 8732 ; free virtual = 43577 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 8722 ; free virtual = 43563 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.914 ; gain = 236.473 ; free physical = 8715 ; free virtual = 43556 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 8710 ; free virtual = 43551 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8696 ; free virtual = 43541 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 8683 ; free virtual = 43524 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 8688 ; free virtual = 43529 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 8655 ; free virtual = 43496 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 8622 ; free virtual = 43463 Phase 2 Global Placement Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: fe41f556 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8418 ; free virtual = 43259 Phase 3 Initial Routing INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8397 ; free virtual = 43238 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8397 ; free virtual = 43237 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8395 ; free virtual = 43235 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8394 ; free virtual = 43235 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8393 ; free virtual = 43234 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8393 ; free virtual = 43234 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8393 ; free virtual = 43234 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8393 ; free virtual = 43234 --------------------------------------------------------------------------------- Phase 6 Post Hold Fix | Checksum: e279f4d5 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8393 ; free virtual = 43234 --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8393 ; free virtual = 43234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8392 ; free virtual = 43233 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8390 ; free virtual = 43231 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Phase 7 Route finalize Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8387 ; free virtual = 43228 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.930 ; gain = 246.488 ; free physical = 8381 ; free virtual = 43222 Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 8381 ; free virtual = 43222 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e279f4d5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8359 ; free virtual = 43200 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e279f4d5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8357 ; free virtual = 43198 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: e279f4d5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8351 ; free virtual = 43192 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.230 ; gain = 16.688 ; free physical = 8387 ; free virtual = 43228 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:46 . Memory (MB): peak = 2141.020 ; gain = 55.477 ; free physical = 8387 ; free virtual = 43228 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 8359 ; free virtual = 43200 Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2141.020 ; gain = 0.000 ; free physical = 8344 ; free virtual = 43187 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 8324 ; free virtual = 43165 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 8304 ; free virtual = 43145 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 8279 ; free virtual = 43120 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 8264 ; free virtual = 43105 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 8283 ; free virtual = 43124 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 8284 ; free virtual = 43125 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 8284 ; free virtual = 43125 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 8223 ; free virtual = 43064 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 8182 ; free virtual = 43023 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 8133 ; free virtual = 42975 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 8071 ; free virtual = 42912 Phase 3.4 Pipeline Register Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 8087 ; free virtual = 42928 Phase 3.5 Small Shape Detail Placement INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 8106 ; free virtual = 42948 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7715 ; free virtual = 42557 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7710 ; free virtual = 42552 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1424.930 ; gain = 342.047 ; free physical = 7721 ; free virtual = 42562 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 7706 ; free virtual = 42547 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7669 ; free virtual = 42510 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7623 ; free virtual = 42464 Phase 3.7 Pipeline Register Optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 7619 ; free virtual = 42461 Phase 1.3 Build Placer Netlist Model Loading data files... Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 7605 ; free virtual = 42447 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 7605 ; free virtual = 42446 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 7603 ; free virtual = 42445 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 7606 ; free virtual = 42448 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 7649 ; free virtual = 42491 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 7649 ; free virtual = 42490 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7645 ; free virtual = 42486 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7577 ; free virtual = 42419 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7594 ; free virtual = 42436 Phase 4.2 Post Placement Cleanup Phase 1 Build RT Design | Checksum: 1a631b8be Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2133.070 ; gain = 48.668 ; free physical = 7562 ; free virtual = 42403 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 7537 ; free virtual = 42379 --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7528 ; free virtual = 42369 Phase 4.3 Placer Reporting Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 7493 ; free virtual = 42334 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cf4d1b03 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1488.961 ; gain = 0.000 ; free physical = 7487 ; free virtual = 42328 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7453 ; free virtual = 42294 Phase 4.4 Final Placement Cleanup Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 7446 ; free virtual = 42288 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2143.059 ; gain = 58.656 ; free physical = 7446 ; free virtual = 42287 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a631b8be Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2143.059 ; gain = 58.656 ; free physical = 7493 ; free virtual = 42334 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7513 ; free virtual = 42355 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7505 ; free virtual = 42346 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7506 ; free virtual = 42348 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2107.211 ; gain = 557.254 ; free physical = 7515 ; free virtual = 42357 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2107.211 ; gain = 639.957 ; free physical = 7514 ; free virtual = 42355 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7442 ; free virtual = 42283 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7424 ; free virtual = 42265 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7420 ; free virtual = 42262 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7408 ; free virtual = 42249 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7408 ; free virtual = 42249 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7407 ; free virtual = 42248 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7407 ; free virtual = 42248 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7407 ; free virtual = 42248 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7403 ; free virtual = 42245 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 7404 ; free virtual = 42245 INFO: [Project 1-571] Translating synthesized netlist Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7398 ; free virtual = 42239 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7393 ; free virtual = 42235 Phase 4 Rip-up And Reroute | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7394 ; free virtual = 42236 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7382 ; free virtual = 42223 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7380 ; free virtual = 42221 Phase 6 Post Hold Fix | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7379 ; free virtual = 42221 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7380 ; free virtual = 42222 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18b270a8f Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7378 ; free virtual = 42219 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18b270a8f Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7344 ; free virtual = 42186 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.488 ; gain = 94.086 ; free physical = 7387 ; free virtual = 42229 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:48 . Memory (MB): peak = 2217.277 ; gain = 164.891 ; free physical = 7378 ; free virtual = 42220 Writing placer database... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.277 ; gain = 0.000 ; free physical = 7199 ; free virtual = 42068 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 7046 ; free virtual = 41890 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 6835 ; free virtual = 41680 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 6834 ; free virtual = 41679 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7508 Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6617 ; free virtual = 41461 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6581 ; free virtual = 41425 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6580 ; free virtual = 41424 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 100878403 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6457 ; free virtual = 41301 Phase 3 Initial Routing WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6471 ; free virtual = 41316 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6462 ; free virtual = 41306 Phase 4 Rip-up And Reroute | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6467 ; free virtual = 41311 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6467 ; free virtual = 41311 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6467 ; free virtual = 41311 Phase 6 Post Hold Fix | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6467 ; free virtual = 41311 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6411 ; free virtual = 41256 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6409 ; free virtual = 41254 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: e4c05920 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6438 ; free virtual = 41282 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6475 ; free virtual = 41319 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2139.020 ; gain = 46.473 ; free physical = 6473 ; free virtual = 41318 Phase 1 Build RT Design | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6459 ; free virtual = 41304 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing placer database... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6419 ; free virtual = 41264 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6418 ; free virtual = 41263 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2139.020 ; gain = 0.000 ; free physical = 6401 ; free virtual = 41248 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4ae2ab4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6149 ; free virtual = 40994 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130e541f3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6129 ; free virtual = 40974 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6139 ; free virtual = 40984 Phase 4 Rip-up And Reroute | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6142 ; free virtual = 40987 Phase 5 Delay and Skew Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 5 Delay and Skew Optimization | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6144 ; free virtual = 40989 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6148 ; free virtual = 40993 Phase 6 Post Hold Fix | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6149 ; free virtual = 40994 Phase 7 Route finalize Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.449 ; gain = 0.000 ; free physical = 6156 ; free virtual = 41001 Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Command: report_drc (run_mandatory_drcs) for: bitstream_checks Phase 7 Route finalize | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6155 ; free virtual = 41000 Phase 8 Verifying routed nets INFO: [DRC 23-27] Running DRC with 8 threads Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6154 ; free virtual = 40999 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6128 ; free virtual = 40973 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2100.230 ; gain = 7.684 ; free physical = 6161 ; free virtual = 41006 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2139.020 ; gain = 46.473 ; free physical = 6159 ; free virtual = 41004 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2139.020 ; gain = 0.000 ; free physical = 6113 ; free virtual = 40961 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f35ea853 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 6053 ; free virtual = 40899 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 5978 ; free virtual = 40824 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 5948 ; free virtual = 40793 Phase 1 Placer Initialization | Checksum: 18ab10e39 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.492 ; gain = 507.531 ; free physical = 5918 ; free virtual = 40764 Phase 2 Global Placement Running DRC as a precondition to command write_bitstream INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 5811 ; free virtual = 40657 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 5721 ; free virtual = 40567 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5728 ; free virtual = 40573 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5733 ; free virtual = 40578 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5719 ; free virtual = 40565 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5733 ; free virtual = 40578 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5770 ; free virtual = 40615 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 5777 ; free virtual = 40623 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 5777 ; free virtual = 40622 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Writing bitstream ./design.bit... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 5956 ; free virtual = 40806 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 5918 ; free virtual = 40768 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 5921 ; free virtual = 40771 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Device 21-403] Loading part xc7z020clg400-1 Starting Routing Task --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 5965 ; free virtual = 40815 --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5962 ; free virtual = 40812 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 3.1 Commit Multi Column Macros | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5954 ; free virtual = 40804 Phase 3.2 Commit Most Macros & LUTRAMs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 251526ef8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5938 ; free virtual = 40788 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22b2d4cc3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5897 ; free virtual = 40747 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f4e1ad28 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5890 ; free virtual = 40740 Phase 3.5 Small Shape Detail Placement Loading data files... Phase 3.5 Small Shape Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5801 ; free virtual = 40651 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5796 ; free virtual = 40646 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5790 ; free virtual = 40640 Phase 3 Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5784 ; free virtual = 40634 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5770 ; free virtual = 40620 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5761 ; free virtual = 40611 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5756 ; free virtual = 40606 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5751 ; free virtual = 40601 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5745 ; free virtual = 40595 Ending Placer Task | Checksum: 16e2e720d Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.535 ; gain = 595.574 ; free physical = 5749 ; free virtual = 40599 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.535 ; gain = 659.605 ; free physical = 5748 ; free virtual = 40598 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 898ec903 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:49:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2475.125 ; gain = 334.105 ; free physical = 5555 ; free virtual = 40405 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:49:21 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2062.926 ; gain = 44.668 ; free physical = 6306 ; free virtual = 41156 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 6269 ; free virtual = 41119 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 6268 ; free virtual = 41119 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2077.969 ; gain = 59.711 ; free physical = 6210 ; free virtual = 41061 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6201 ; free virtual = 41052 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6190 ; free virtual = 41041 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6190 ; free virtual = 41040 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6189 ; free virtual = 41040 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6180 ; free virtual = 41030 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6180 ; free virtual = 41030 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 6169 ; free virtual = 41020 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.969 ; gain = 63.711 ; free physical = 6168 ; free virtual = 41018 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.969 ; gain = 63.711 ; free physical = 6162 ; free virtual = 41013 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2081.969 ; gain = 63.711 ; free physical = 6196 ; free virtual = 41047 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2120.758 ; gain = 134.516 ; free physical = 6194 ; free virtual = 41045 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2120.758 ; gain = 0.000 ; free physical = 6099 ; free virtual = 40952 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 5738 ; free virtual = 40589 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 5720 ; free virtual = 40571 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5714 ; free virtual = 40566 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 5692 ; free virtual = 40543 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 5631 ; free virtual = 40482 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 5619 ; free virtual = 40470 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 5617 ; free virtual = 40468 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 5612 ; free virtual = 40463 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 5611 ; free virtual = 40461 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 5601 ; free virtual = 40452 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 5600 ; free virtual = 40451 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5553 ; free virtual = 40404 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5554 ; free virtual = 40405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5554 ; free virtual = 40405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5554 ; free virtual = 40405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5551 ; free virtual = 40402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5551 ; free virtual = 40402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5549 ; free virtual = 40400 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 5548 ; free virtual = 40399 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 5551 ; free virtual = 40402 INFO: [Project 1-571] Translating synthesized netlist Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 5107 ; free virtual = 39958 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 5094 ; free virtual = 39945 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 5054 ; free virtual = 39905 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 5054 ; free virtual = 39905 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4991 ; free virtual = 39842 Phase 3 Initial Routing Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4961 ; free virtual = 39812 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4961 ; free virtual = 39812 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4961 ; free virtual = 39812 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4961 ; free virtual = 39812 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4961 ; free virtual = 39812 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 4961 ; free virtual = 39812 Phase 7 Route finalize report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Starting Placer Task Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 4957 ; free virtual = 39808 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 4957 ; free virtual = 39808 Phase 9 Depositing Routes INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 4957 ; free virtual = 39808 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 4957 ; free virtual = 39808 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 4956 ; free virtual = 39807 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 4994 ; free virtual = 39845 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 4994 ; free virtual = 39845 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 4979 ; free virtual = 39834 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.965 ; gain = 22.754 ; free physical = 5032 ; free virtual = 39888 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.953 ; gain = 28.742 ; free physical = 5067 ; free virtual = 39922 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.953 ; gain = 28.742 ; free physical = 5065 ; free virtual = 39921 Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4943 ; free virtual = 39799 Phase 3 Initial Routing Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2061.926 ; gain = 43.668 ; free physical = 4885 ; free virtual = 39740 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 4854 ; free virtual = 39710 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 4854 ; free virtual = 39710 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4923 ; free virtual = 39779 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4916 ; free virtual = 39772 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4916 ; free virtual = 39772 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4916 ; free virtual = 39772 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4916 ; free virtual = 39772 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4916 ; free virtual = 39772 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4895 ; free virtual = 39751 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4893 ; free virtual = 39749 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4889 ; free virtual = 39745 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.008 ; gain = 47.797 ; free physical = 4922 ; free virtual = 39777 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2193.797 ; gain = 86.586 ; free physical = 4921 ; free virtual = 39776 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 4912 ; free virtual = 39768 Phase 3 Initial Routing Writing placer database... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4874 ; free virtual = 39732 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4874 ; free virtual = 39732 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4874 ; free virtual = 39732 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4874 ; free virtual = 39732 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4873 ; free virtual = 39731 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4873 ; free virtual = 39731 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 4887 ; free virtual = 39747 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 4888 ; free virtual = 39747 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 4884 ; free virtual = 39744 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 4921 ; free virtual = 39781 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2121.758 ; gain = 135.516 ; free physical = 4917 ; free virtual = 39778 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 4879 ; free virtual = 39743 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Loading data files... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:49:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading site data... 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2473.125 ; gain = 334.105 ; free physical = 5429 ; free virtual = 40308 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:49:48 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.797 ; gain = 0.000 ; free physical = 6318 ; free virtual = 41206 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:49:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:06 ; elapsed = 00:00:50 . Memory (MB): peak = 2607.398 ; gain = 390.121 ; free physical = 6296 ; free virtual = 41162 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:49:51 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:49:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2474.125 ; gain = 335.105 ; free physical = 7381 ; free virtual = 42246 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:49:52 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8936 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... Loading data files... Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 7690 ; free virtual = 42571 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 7721 ; free virtual = 42603 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 7720 ; free virtual = 42601 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 7720 ; free virtual = 42601 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 7720 ; free virtual = 42601 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 7719 ; free virtual = 42600 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 7720 ; free virtual = 42601 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 7720 ; free virtual = 42601 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2460.863 ; gain = 340.105 ; free physical = 7628 ; free virtual = 42510 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:02 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 8369 ; free virtual = 43255 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 8634 ; free virtual = 43526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 8635 ; free virtual = 43527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 8631 ; free virtual = 43523 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 8591 ; free virtual = 43483 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2463.430 ; gain = 335.176 ; free physical = 8602 ; free virtual = 43493 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:07 2019... Phase 1 Build RT Design | Checksum: cea32407 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 8534 ; free virtual = 43425 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: cea32407 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 8521 ; free virtual = 43412 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: cea32407 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 8523 ; free virtual = 43415 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2087.375 ; gain = 62.086 ; free physical = 9314 ; free virtual = 44206 Phase 3 Initial Routing Loading route data... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9271 ; free virtual = 44163 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9269 ; free virtual = 44161 Phase 4 Rip-up And Reroute | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9268 ; free virtual = 44161 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9268 ; free virtual = 44160 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9266 ; free virtual = 44158 Phase 6 Post Hold Fix | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9266 ; free virtual = 44158 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2089.375 ; gain = 64.086 ; free physical = 9247 ; free virtual = 44139 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2091.375 ; gain = 66.086 ; free physical = 9245 ; free virtual = 44137 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1bf4d4050 Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2091.375 ; gain = 66.086 ; free physical = 9246 ; free virtual = 44138 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2091.375 ; gain = 66.086 ; free physical = 9284 ; free virtual = 44176 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:53 . Memory (MB): peak = 2130.164 ; gain = 136.891 ; free physical = 9286 ; free virtual = 44178 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.70 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 9287 ; free virtual = 44183 Phase 1 Build RT Design | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 9219 ; free virtual = 44115 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 9181 ; free virtual = 44078 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1e03090e9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2084.535 ; gain = 0.000 ; free physical = 9181 ; free virtual = 44078 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 129e3aa92 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9070 ; free virtual = 43963 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9126 ; free virtual = 44019 Command: report_drc (run_mandatory_drcs) for: bitstream_checks ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } INFO: [DRC 23-27] Running DRC with 8 threads ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Creating bitstream... Phase 4.1 Global Iteration 0 | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9126 ; free virtual = 44019 Phase 4 Rip-up And Reroute | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9126 ; free virtual = 44018 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9126 ; free virtual = 44019 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9128 ; free virtual = 44021 Phase 6 Post Hold Fix | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9125 ; free virtual = 44018 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9092 ; free virtual = 43984 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9090 ; free virtual = 43983 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b51bc211 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9067 ; free virtual = 43960 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2102.223 ; gain = 17.688 ; free physical = 9102 ; free virtual = 43995 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2141.012 ; gain = 56.477 ; free physical = 9101 ; free virtual = 43994 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2141.012 ; gain = 0.000 ; free physical = 9077 ; free virtual = 43972 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9361 Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } No constraint files found. ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 9489 ; free virtual = 44391 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 9454 ; free virtual = 44356 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9424 ; free virtual = 44326 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9299 ; free virtual = 44201 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9297 ; free virtual = 44198 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9291 ; free virtual = 44193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9291 ; free virtual = 44193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9291 ; free virtual = 44192 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9291 ; free virtual = 44192 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9291 ; free virtual = 44192 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 9290 ; free virtual = 44192 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9290 ; free virtual = 44192 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9440 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2459.863 ; gain = 338.105 ; free physical = 9137 ; free virtual = 44039 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:18 2019... Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9482 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2062.926 ; gain = 43.668 ; free physical = 10025 ; free virtual = 44927 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 10010 ; free virtual = 44911 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 10010 ; free virtual = 44911 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2532.902 ; gain = 339.105 ; free physical = 9948 ; free virtual = 44850 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:19 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2081.094 ; gain = 61.836 ; free physical = 9939 ; free virtual = 44841 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 11004 ; free virtual = 45906 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 10994 ; free virtual = 45896 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 10993 ; free virtual = 45894 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 10991 ; free virtual = 45893 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 10990 ; free virtual = 45891 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 10989 ; free virtual = 45890 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2083.094 ; gain = 63.836 ; free physical = 10954 ; free virtual = 45856 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.094 ; gain = 65.836 ; free physical = 10951 ; free virtual = 45853 Phase 9 Depositing Routes touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.094 ; gain = 65.836 ; free physical = 10945 ; free virtual = 45848 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2085.094 ; gain = 65.836 ; free physical = 10977 ; free virtual = 45880 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:53 . Memory (MB): peak = 2123.883 ; gain = 136.641 ; free physical = 10976 ; free virtual = 45878 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2123.883 ; gain = 0.000 ; free physical = 10923 ; free virtual = 45827 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 10847 ; free virtual = 45749 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 10752 ; free virtual = 45656 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 10752 ; free virtual = 45656 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10774 ; free virtual = 45677 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10526 ; free virtual = 45430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10534 ; free virtual = 45438 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10533 ; free virtual = 45437 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10521 ; free virtual = 45425 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 10261 ; free virtual = 45165 --------------------------------------------------------------------------------- Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9670 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 10052 ; free virtual = 44956 --------------------------------------------------------------------------------- Loading site data... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] Loading route data... WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] Processing options... WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] Creating bitmap... WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9717 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9443 ; free virtual = 44347 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9497 ; free virtual = 44401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9495 ; free virtual = 44399 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ Creating bitstream... | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9460 ; free virtual = 44364 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9460 ; free virtual = 44364 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9457 ; free virtual = 44362 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9457 ; free virtual = 44362 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9457 ; free virtual = 44361 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9456 ; free virtual = 44360 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9447 ; free virtual = 44351 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9447 ; free virtual = 44351 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 9449 ; free virtual = 44353 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9779 ; free virtual = 44691 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 9422 ; free virtual = 44334 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 2475.117 ; gain = 334.105 ; free physical = 9514 ; free virtual = 44431 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:42 2019... 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.270 ; gain = 340.105 ; free physical = 9533 ; free virtual = 44451 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:42 2019... 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 9544 ; free virtual = 44463 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Config size: 1060815 words Number of configuration frames: 9996 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9823 DONE DONE INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 11263 ; free virtual = 46197 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 11306 ; free virtual = 46220 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_009/OK INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 11291 ; free virtual = 46207 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 11264 ; free virtual = 46185 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: Launching helper process for spawning children vivado processes INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1343] INFO: Helper process launched with PID 9895 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 11179 ; free virtual = 46114 Phase 1.3 Build Placer Netlist Model Creating bitstream... Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 11194 ; free virtual = 46130 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 11194 ; free virtual = 46130 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 11197 ; free virtual = 46133 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 11199 ; free virtual = 46135 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 11204 ; free virtual = 46140 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 11205 ; free virtual = 46141 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11267 ; free virtual = 46208 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 11261 ; free virtual = 46203 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 11269 ; free virtual = 46219 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 11268 ; free virtual = 46219 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 11260 ; free virtual = 46207 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 11261 ; free virtual = 46209 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.953 ; gain = 115.504 ; free physical = 11245 ; free virtual = 46181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 11243 ; free virtual = 46179 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 11242 ; free virtual = 46179 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11232 ; free virtual = 46169 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 11204 ; free virtual = 46122 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11205 ; free virtual = 46123 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11198 ; free virtual = 46116 Phase 4 Rip-up And Reroute | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11197 ; free virtual = 46116 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11197 ; free virtual = 46116 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11198 ; free virtual = 46117 Phase 6 Post Hold Fix | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11198 ; free virtual = 46117 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 11201 ; free virtual = 46120 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 11201 ; free virtual = 46120 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 11206 ; free virtual = 46125 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 11241 ; free virtual = 46160 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 11242 ; free virtual = 46161 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing placer database... Writing XDEF routing. Starting Routing Task Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 11213 ; free virtual = 46152 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 11058 ; free virtual = 45977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1333.102 ; gain = 237.184 ; free physical = 11058 ; free virtual = 45977 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 11257 ; free virtual = 46180 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:50:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.988 ; gain = 338.105 ; free physical = 11087 ; free virtual = 46010 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:50:52 2019... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11245 ; free virtual = 46168 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 1337.070 ; gain = 241.152 ; free physical = 11798 ; free virtual = 46722 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 11749 ; free virtual = 46673 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 11732 ; free virtual = 46656 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11720 ; free virtual = 46644 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11734 ; free virtual = 46658 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11699 ; free virtual = 46623 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11698 ; free virtual = 46622 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11689 ; free virtual = 46613 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 11674 ; free virtual = 46597 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11686 ; free virtual = 46616 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11683 ; free virtual = 46614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1338.105 ; gain = 242.184 ; free physical = 11683 ; free virtual = 46613 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11680 ; free virtual = 46611 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11678 ; free virtual = 46610 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11675 ; free virtual = 46608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11675 ; free virtual = 46607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11674 ; free virtual = 46607 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 11671 ; free virtual = 46605 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 11671 ; free virtual = 46605 INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1338.105 ; gain = 242.184 ; free physical = 11605 ; free virtual = 46549 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11587 ; free virtual = 46513 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.102 ; gain = 251.184 ; free physical = 11619 ; free virtual = 46544 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.102 ; gain = 251.184 ; free physical = 11584 ; free virtual = 46529 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11526 ; free virtual = 46471 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 11348 ; free virtual = 46273 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 11346 ; free virtual = 46272 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11342 ; free virtual = 46268 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11356 ; free virtual = 46281 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11408 ; free virtual = 46334 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11381 ; free virtual = 46307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11374 ; free virtual = 46300 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11372 ; free virtual = 46298 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11372 ; free virtual = 46297 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11371 ; free virtual = 46297 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 11368 ; free virtual = 46294 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1346.090 ; gain = 250.160 ; free physical = 11370 ; free virtual = 46296 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:16] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11289 ; free virtual = 46215 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11268 ; free virtual = 46193 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:7] --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11157 ; free virtual = 46083 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11194 ; free virtual = 46120 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11206 ; free virtual = 46132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11207 ; free virtual = 46134 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11208 ; free virtual = 46136 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1355.078 ; gain = 259.160 ; free physical = 11198 ; free virtual = 46127 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1355.086 ; gain = 259.160 ; free physical = 11197 ; free virtual = 46126 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11150 ; free virtual = 46076 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 11085 ; free virtual = 46012 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 11084 ; free virtual = 46010 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Device 21-403] Loading part xc7z020clg400-1 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 11094 ; free virtual = 46021 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Loading site data... INFO: [Timing 38-35] Done setting XDC timing constraints. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10701 ; free virtual = 45627 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: eeeca7b0 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 10699 ; free virtual = 45625 Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10687 ; free virtual = 45614 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 10689 ; free virtual = 45616 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10671 ; free virtual = 45597 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10671 ; free virtual = 45598 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 10635 ; free virtual = 45561 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 10631 ; free virtual = 45557 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 10626 ; free virtual = 45552 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 10623 ; free virtual = 45550 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 10623 ; free virtual = 45549 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 10634 ; free virtual = 45561 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 10635 ; free virtual = 45561 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 1335.070 ; gain = 239.152 ; free physical = 10643 ; free virtual = 45569 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10590 ; free virtual = 45516 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10587 ; free virtual = 45513 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10587 ; free virtual = 45513 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10588 ; free virtual = 45514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10588 ; free virtual = 45515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10588 ; free virtual = 45514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10589 ; free virtual = 45515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10588 ; free virtual = 45514 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10588 ; free virtual = 45514 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 10589 ; free virtual = 45515 Creating bitstream... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Project 1-571] Translating synthesized netlist WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-570] Preparing netlist for logic optimization Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10204 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1345.102 ; gain = 249.184 ; free physical = 10362 ; free virtual = 45288 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Command: synth_design -top top No constraint files found. Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1345.102 ; gain = 249.184 ; free physical = 10352 ; free virtual = 45282 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10245 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:42 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10368 ; free virtual = 45298 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 10392 ; free virtual = 45323 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.555 ; gain = 247.938 ; free physical = 10348 ; free virtual = 45278 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1343.555 ; gain = 247.938 ; free physical = 10334 ; free virtual = 45264 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10312 ; free virtual = 45242 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10311 ; free virtual = 45241 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10302 ; free virtual = 45232 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10297 ; free virtual = 45228 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10297 ; free virtual = 45227 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10278 ; free virtual = 45209 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10272 ; free virtual = 45202 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10267 ; free virtual = 45197 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10265 ; free virtual = 45195 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10264 ; free virtual = 45194 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 10261 ; free virtual = 45192 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1353.086 ; gain = 257.160 ; free physical = 10263 ; free virtual = 45194 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10205 ; free virtual = 45135 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10203 ; free virtual = 45134 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10198 ; free virtual = 45128 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10197 ; free virtual = 45128 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10197 ; free virtual = 45127 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10196 ; free virtual = 45127 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10196 ; free virtual = 45126 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 10197 ; free virtual = 45127 Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 1364.586 ; gain = 268.961 ; free physical = 10198 ; free virtual = 45128 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:51:12 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Project 1-571] Translating synthesized netlist 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 10187 ; free virtual = 45117 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:51:12 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10382 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10886 ; free virtual = 45817 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 10746 ; free virtual = 45677 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10767 ; free virtual = 45698 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10747 ; free virtual = 45678 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10746 ; free virtual = 45677 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10733 ; free virtual = 45664 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10346 ; free virtual = 45277 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 10293 ; free virtual = 45225 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10296 ; free virtual = 45227 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 10302 ; free virtual = 45233 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:05 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 10314 ; free virtual = 45245 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 10264 ; free virtual = 45195 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 10303 ; free virtual = 45234 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b1503975 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10247 ; free virtual = 45178 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10247 ; free virtual = 45178 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10227 ; free virtual = 45158 Phase 1 Placer Initialization | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 10226 ; free virtual = 45158 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 10086 ; free virtual = 45020 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.60 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 10102 ; free virtual = 45036 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1559.863 ; gain = 0.000 ; free physical = 10045 ; free virtual = 44980 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.70 . Memory (MB): peak = 1559.863 ; gain = 0.000 ; free physical = 10014 ; free virtual = 44948 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 10003 ; free virtual = 44938 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 9881 ; free virtual = 44815 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9778 ; free virtual = 44712 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2408ba81e Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9773 ; free virtual = 44708 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2559e6f74 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9767 ; free virtual = 44702 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22f794d3f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9688 ; free virtual = 44628 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f92dada4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9675 ; free virtual = 44610 Phase 3.5 Small Shape Detail Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 9557 ; free virtual = 44492 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9518 ; free virtual = 44452 Phase 3.6 Re-assign LUT pins Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 9518 ; free virtual = 44452 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9515 ; free virtual = 44449 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9489 ; free virtual = 44424 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9486 ; free virtual = 44421 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 3 Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9524 ; free virtual = 44459 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9565 ; free virtual = 44503 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9573 ; free virtual = 44515 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9580 ; free virtual = 44523 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9584 ; free virtual = 44531 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143725fd8 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9581 ; free virtual = 44530 Ending Placer Task | Checksum: fb45469f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 9591 ; free virtual = 44543 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 9591 ; free virtual = 44543 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 9591 ; free virtual = 44540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 9875 ; free virtual = 44835 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 9874 ; free virtual = 44834 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 9861 ; free virtual = 44821 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9845 ; free virtual = 44805 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9845 ; free virtual = 44805 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9844 ; free virtual = 44804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9844 ; free virtual = 44804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9843 ; free virtual = 44803 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9842 ; free virtual = 44802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9841 ; free virtual = 44800 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 9837 ; free virtual = 44797 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 9838 ; free virtual = 44797 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Phase 1 Build RT Design | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2058.930 ; gain = 94.668 ; free physical = 9754 ; free virtual = 44714 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1553.859 ; gain = 0.000 ; free physical = 9736 ; free virtual = 44696 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 9714 ; free virtual = 44673 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 126a650e7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 9714 ; free virtual = 44673 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.51 . Memory (MB): peak = 1553.859 ; gain = 0.000 ; free physical = 9726 ; free virtual = 44686 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9696 ; free virtual = 44658 Phase 3 Initial Routing Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-570] Preparing netlist for logic optimization Checksum: PlaceDB: 16a59d95 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9673 ; free virtual = 44633 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9667 ; free virtual = 44627 Phase 4 Rip-up And Reroute | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9667 ; free virtual = 44627 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9667 ; free virtual = 44627 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9666 ; free virtual = 44626 Phase 6 Post Hold Fix | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 9666 ; free virtual = 44626 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.570 ; gain = 215.121 ; free physical = 9590 ; free virtual = 44550 --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 9588 ; free virtual = 44548 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 9584 ; free virtual = 44544 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 96eb7d44 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 9581 ; free virtual = 44541 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 9609 ; free virtual = 44569 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 9606 ; free virtual = 44566 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 9498 ; free virtual = 44459 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.570 ; gain = 215.121 ; free physical = 9439 ; free virtual = 44399 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9410 ; free virtual = 44370 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 9385 ; free virtual = 44345 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9377 ; free virtual = 44337 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9371 ; free virtual = 44332 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9367 ; free virtual = 44328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9367 ; free virtual = 44328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9366 ; free virtual = 44327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9365 ; free virtual = 44325 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9364 ; free virtual = 44324 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9360 ; free virtual = 44320 Phase 1.3 Build Placer Netlist Model Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.562 ; gain = 225.113 ; free physical = 9360 ; free virtual = 44320 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.570 ; gain = 225.113 ; free physical = 9362 ; free virtual = 44322 Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9360 ; free virtual = 44320 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-571] Translating synthesized netlist Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9355 ; free virtual = 44315 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9354 ; free virtual = 44314 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9348 ; free virtual = 44309 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 9349 ; free virtual = 44309 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 9350 ; free virtual = 44310 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9235 ; free virtual = 44196 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 9101 ; free virtual = 44061 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 9097 ; free virtual = 44057 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully Command: synth_design -top top synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 9069 ; free virtual = 44030 Command: place_design Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: Helper process launched with PID 11369 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9045 ; free virtual = 44005 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 8985 ; free virtual = 43946 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8972 ; free virtual = 43932 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8812 ; free virtual = 43772 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8808 ; free virtual = 43768 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8805 ; free virtual = 43765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8802 ; free virtual = 43762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8800 ; free virtual = 43761 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8800 ; free virtual = 43760 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8801 ; free virtual = 43761 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 8798 ; free virtual = 43758 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 8798 ; free virtual = 43758 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 8688 ; free virtual = 43649 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 8667 ; free virtual = 43627 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.602 ; gain = 333.711 ; free physical = 8624 ; free virtual = 43584 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.633 ; gain = 0.000 ; free physical = 8546 ; free virtual = 43506 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.633 ; gain = 0.000 ; free physical = 8530 ; free virtual = 43490 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 7897 ; free virtual = 42857 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1904.441 ; gain = 0.000 ; free physical = 7870 ; free virtual = 42830 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 7566 ; free virtual = 42527 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 7569 ; free virtual = 42529 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 7568 ; free virtual = 42528 Loading site data... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7552 ; free virtual = 42512 Phase 1.3 Build Placer Netlist Model Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 7540 ; free virtual = 42501 Loading route data... Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 7477 ; free virtual = 42437 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 7435 ; free virtual = 42396 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 7434 ; free virtual = 42394 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 7363 ; free virtual = 42323 Phase 3 Initial Routing INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 7361 ; free virtual = 42322 --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7368 ; free virtual = 42329 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7378 ; free virtual = 42339 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7377 ; free virtual = 42338 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7376 ; free virtual = 42337 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7373 ; free virtual = 42336 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7371 ; free virtual = 42335 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 7366 ; free virtual = 42327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 7365 ; free virtual = 42326 --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 7339 ; free virtual = 42299 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 7320 ; free virtual = 42281 Phase 8 Verifying routed nets Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 7321 ; free virtual = 42281 Phase 9 Depositing Routes Creating bitstream... Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 7346 ; free virtual = 42306 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 7382 ; free virtual = 42343 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 7382 ; free virtual = 42342 Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 7357 ; free virtual = 42318 Phase 1.3 Build Placer Netlist Model Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 7139 ; free virtual = 42103 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7080 ; free virtual = 42041 Phase 1.4 Constrain Clocks/Macros Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7093 ; free virtual = 42054 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 7176 ; free virtual = 42138 Phase 2 Global Placement Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 7167 ; free virtual = 42128 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 498.531 ; free physical = 7196 ; free virtual = 42162 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 7072 ; free virtual = 42038 Phase 1.4 Constrain Clocks/Macros INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 7057 ; free virtual = 42023 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 7031 ; free virtual = 41996 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 6989 ; free virtual = 41955 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 6978 ; free virtual = 41944 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Ending Placer Task | Checksum: 110ed1b10 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7007 ; free virtual = 41972 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 7007 ; free virtual = 41972 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 7001 ; free virtual = 41967 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 6964 ; free virtual = 41930 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6954 ; free virtual = 41920 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6953 ; free virtual = 41919 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6952 ; free virtual = 41917 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6949 ; free virtual = 41914 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6950 ; free virtual = 41915 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 6951 ; free virtual = 41917 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 6951 ; free virtual = 41917 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 6921 ; free virtual = 41886 Phase 3.3 Area Swap Optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:51:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2452.867 ; gain = 342.105 ; free physical = 6895 ; free virtual = 41861 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:51:56 2019... Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 6892 ; free virtual = 41858 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 6981 ; free virtual = 41946 Phase 3.5 Small Shape Detail Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 7711 ; free virtual = 42677 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 7656 ; free virtual = 42621 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7631 ; free virtual = 42596 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7682 ; free virtual = 42647 Phase 3.6 Re-assign LUT pins Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 498.531 ; free physical = 7670 ; free virtual = 42635 Phase 1.4 Constrain Clocks/Macros Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7655 ; free virtual = 42620 Phase 3.7 Pipeline Register Optimization Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 498.531 ; free physical = 7622 ; free virtual = 42588 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7630 ; free virtual = 42595 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 498.531 ; free physical = 7596 ; free virtual = 42562 Phase 2 Final Placement Cleanup Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7564 ; free virtual = 42529 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7574 ; free virtual = 42540 --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 498.531 ; free physical = 7574 ; free virtual = 42539 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7574 ; free virtual = 42539 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7578 ; free virtual = 42543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7577 ; free virtual = 42543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7578 ; free virtual = 42543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7577 ; free virtual = 42543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7578 ; free virtual = 42543 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 7581 ; free virtual = 42547 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 7585 ; free virtual = 42550 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 INFO: [Project 1-571] Translating synthesized netlist Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7578 ; free virtual = 42544 Phase 4.2 Post Placement Cleanup Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 498.531 ; free physical = 7573 ; free virtual = 42539 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 7544 ; free virtual = 42509 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7506 ; free virtual = 42471 Phase 4.3 Placer Reporting Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7417 ; free virtual = 42382 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7330 ; free virtual = 42296 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7234 ; free virtual = 42199 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 7164 ; free virtual = 42130 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 7165 ; free virtual = 42130 INFO: [Timing 38-35] Done setting XDC timing constraints. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.121 ; gain = 0.000 ; free physical = 7024 ; free virtual = 41990 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 7031 ; free virtual = 41996 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.164 ; gain = 511.531 ; free physical = 7068 ; free virtual = 42034 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.164 ; gain = 511.531 ; free physical = 7067 ; free virtual = 42032 Phase 1.4 Constrain Clocks/Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.164 ; gain = 511.531 ; free physical = 7067 ; free virtual = 42032 Starting Routing Task Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.164 ; gain = 511.531 ; free physical = 7066 ; free virtual = 42031 Phase 2 Final Placement Cleanup INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.164 ; gain = 511.531 ; free physical = 7065 ; free virtual = 42031 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.164 ; gain = 511.531 ; free physical = 7066 ; free virtual = 42032 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.164 ; gain = 577.562 ; free physical = 7066 ; free virtual = 42032 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 6729 ; free virtual = 41694 Phase 1.3 Build Placer Netlist Model Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 6357 ; free virtual = 41323 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 6357 ; free virtual = 41322 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6349 ; free virtual = 41314 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6340 ; free virtual = 41306 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6339 ; free virtual = 41305 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6340 ; free virtual = 41306 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6339 ; free virtual = 41305 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6338 ; free virtual = 41304 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 6338 ; free virtual = 41304 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 6309 ; free virtual = 41275 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 6308 ; free virtual = 41274 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 6223 ; free virtual = 41189 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 6210 ; free virtual = 41176 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 6203 ; free virtual = 41168 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 6195 ; free virtual = 41160 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 6213 ; free virtual = 41178 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 6213 ; free virtual = 41178 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6056 ; free virtual = 41024 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6017 ; free virtual = 40986 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 6015 ; free virtual = 40984 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174587064 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6207 ; free virtual = 41176 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6180 ; free virtual = 41150 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6179 ; free virtual = 41149 Phase 4 Rip-up And Reroute | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6179 ; free virtual = 41149 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6179 ; free virtual = 41149 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6179 ; free virtual = 41149 Phase 6 Post Hold Fix | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6178 ; free virtual = 41148 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 7 Route finalize Phase 1 Build RT Design Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6208 ; free virtual = 41178 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6197 ; free virtual = 41167 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6176 ; free virtual = 41146 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 6206 ; free virtual = 41176 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 6195 ; free virtual = 41165 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 6125 ; free virtual = 41097 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:52:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2472.363 ; gain = 344.105 ; free physical = 6149 ; free virtual = 41119 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:52:17 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 7024 ; free virtual = 41994 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 6976 ; free virtual = 41947 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12e08b258 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 6976 ; free virtual = 41946 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 106d813e1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6927 ; free virtual = 41898 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6844 ; free virtual = 41814 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6856 ; free virtual = 41826 Phase 4 Rip-up And Reroute | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6857 ; free virtual = 41827 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6860 ; free virtual = 41830 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6861 ; free virtual = 41831 Phase 6 Post Hold Fix | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6862 ; free virtual = 41832 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 106d813e1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 6861 ; free virtual = 41832 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 106d813e1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6860 ; free virtual = 41830 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 106d813e1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6862 ; free virtual = 41832 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6909 ; free virtual = 41880 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 6912 ; free virtual = 41882 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 6888 ; free virtual = 41860 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12687 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 6033 ; free virtual = 41003 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6008 ; free virtual = 40978 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6008 ; free virtual = 40978 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6006 ; free virtual = 40977 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6005 ; free virtual = 40975 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6003 ; free virtual = 40974 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 6002 ; free virtual = 40973 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 6002 ; free virtual = 40973 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 5665 ; free virtual = 40636 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 5555 ; free virtual = 40527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 5540 ; free virtual = 40511 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 5540 ; free virtual = 40511 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 5539 ; free virtual = 40510 --------------------------------------------------------------------------------- Loading site data... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12792 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... Phase 1 Build RT Design | Checksum: 1577c780a Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2135.078 ; gain = 50.668 ; free physical = 5587 ; free virtual = 40567 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1577c780a Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 5820 ; free virtual = 40799 Phase 2.2 Pre Route Cleanup Phase 1 Build RT Design | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 5819 ; free virtual = 40798 Phase 2.2 Pre Route Cleanup | Checksum: 1577c780a Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 5819 ; free virtual = 40798 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 5756 ; free virtual = 40736 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 5756 ; free virtual = 40735 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5769 ; free virtual = 40749 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5725 ; free virtual = 40704 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5739 ; free virtual = 40718 Phase 4 Rip-up And Reroute | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5739 ; free virtual = 40718 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5738 ; free virtual = 40718 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5738 ; free virtual = 40718 Phase 6 Post Hold Fix | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5738 ; free virtual = 40717 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Number of Nodes with overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 2 Router Initialization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5733 ; free virtual = 40712 Phase 3 Initial Routing Phase 7 Route finalize | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 5732 ; free virtual = 40712 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 5733 ; free virtual = 40712 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 128d436ff Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 5733 ; free virtual = 40712 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 5766 ; free virtual = 40745 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2112.766 ; gain = 180.516 ; free physical = 5765 ; free virtual = 40745 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2112.766 ; gain = 0.000 ; free physical = 5760 ; free virtual = 40740 Number of Nodes with overlaps = 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3 Initial Routing | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5763 ; free virtual = 40743 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5762 ; free virtual = 40742 Phase 4 Rip-up And Reroute | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5757 ; free virtual = 40736 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5755 ; free virtual = 40735 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5749 ; free virtual = 40731 Phase 6 Post Hold Fix | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5742 ; free virtual = 40726 Phase 7 Route finalize Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5701 ; free virtual = 40681 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5689 ; free virtual = 40668 Phase 9 Depositing Routes No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 5706 ; free virtual = 40685 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:52:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.125 ; gain = 335.105 ; free physical = 5765 ; free virtual = 40745 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:52:47 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 5775 ; free virtual = 40754 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 17ae0cba6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5777 ; free virtual = 40757 Running DRC as a precondition to command write_bitstream INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.996 ; gain = 94.586 ; free physical = 5823 ; free virtual = 40803 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2217.785 ; gain = 165.391 ; free physical = 5823 ; free virtual = 40803 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 5832 ; free virtual = 40812 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:52:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 6780 ; free virtual = 41765 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:52:49 2019... touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6829 ; free virtual = 41815 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6830 ; free virtual = 41817 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6832 ; free virtual = 41819 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6832 ; free virtual = 41819 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6832 ; free virtual = 41819 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6834 ; free virtual = 41822 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6844 ; free virtual = 41831 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 6849 ; free virtual = 41837 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 6850 ; free virtual = 41838 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 1 Build RT Design | Checksum: 15c4992dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.848 ; gain = 41.668 ; free physical = 7666 ; free virtual = 42661 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15c4992dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2074.836 ; gain = 48.656 ; free physical = 7631 ; free virtual = 42627 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15c4992dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2074.836 ; gain = 48.656 ; free physical = 7630 ; free virtual = 42626 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1 Build RT Design | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2137.074 ; gain = 52.668 ; free physical = 7616 ; free virtual = 42614 INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.266 ; gain = 61.086 ; free physical = 7630 ; free virtual = 42629 Phase 3 Initial Routing Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.961 ; gain = 31.758 ; free physical = 7592 ; free virtual = 42592 Phase 2.1 Fix Topology Constraints | Checksum: 1ca097e33 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2147.062 ; gain = 62.656 ; free physical = 7591 ; free virtual = 42592 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.2 Pre Route Cleanup Phase 2.1 Fix Topology Constraints Phase 2.2 Pre Route Cleanup | Checksum: 1ca097e33 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2147.062 ; gain = 62.656 ; free physical = 7558 ; free virtual = 42559 Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 7548 ; free virtual = 42550 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 7548 ; free virtual = 42549 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7513 ; free virtual = 42516 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7501 ; free virtual = 42504 Phase 4 Rip-up And Reroute | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7497 ; free virtual = 42500 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7494 ; free virtual = 42498 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7491 ; free virtual = 42495 Phase 6 Post Hold Fix | Checksum: 1b213fb45 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7488 ; free virtual = 42491 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b213fb45 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.266 ; gain = 63.086 ; free physical = 7469 ; free virtual = 42476 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b213fb45 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.266 ; gain = 66.086 ; free physical = 7469 ; free virtual = 42475 Phase 9 Depositing Routes Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.785 ; gain = 0.000 ; free physical = 7495 ; free virtual = 42503 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 9 Depositing Routes | Checksum: 1b213fb45 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.266 ; gain = 66.086 ; free physical = 7474 ; free virtual = 42483 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.266 ; gain = 66.086 ; free physical = 7508 ; free virtual = 42516 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2131.055 ; gain = 136.891 ; free physical = 7506 ; free virtual = 42515 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7510 ; free virtual = 42519 Phase 3 Initial Routing Writing placer database... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 7496 ; free virtual = 42505 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Writing XDEF routing. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7519 ; free virtual = 42530 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 2 Router Initialization | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7520 ; free virtual = 42532 Phase 3 Initial Routing Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7519 ; free virtual = 42531 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7519 ; free virtual = 42531 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7521 ; free virtual = 42533 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7521 ; free virtual = 42533 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7521 ; free virtual = 42533 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Write XDEF Complete: Time (s): cpu = 00:00:00.94 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2131.055 ; gain = 0.000 ; free physical = 7520 ; free virtual = 42533 Loading data files... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7523 ; free virtual = 42535 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7518 ; free virtual = 42531 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7516 ; free virtual = 42530 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 7551 ; free virtual = 42565 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2193.793 ; gain = 94.590 ; free physical = 7551 ; free virtual = 42565 Number of Nodes with overlaps = 0 Writing placer database... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.785 ; gain = 0.000 ; free physical = 7575 ; free virtual = 42560 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3 Initial Routing | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7574 ; free virtual = 42559 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7560 ; free virtual = 42546 Phase 4 Rip-up And Reroute | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7537 ; free virtual = 42523 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130bdaadd Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7507 ; free virtual = 42494 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7483 ; free virtual = 42470 Phase 6 Post Hold Fix | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7439 ; free virtual = 42426 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7397 ; free virtual = 42385 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7404 ; free virtual = 42393 Phase 9 Depositing Routes Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 130bdaadd Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7438 ; free virtual = 42429 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 7477 ; free virtual = 42468 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:54 . Memory (MB): peak = 2217.781 ; gain = 165.391 ; free physical = 7478 ; free virtual = 42469 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 7444 ; free virtual = 42444 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 7406 ; free virtual = 42409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 7419 ; free virtual = 42422 --------------------------------------------------------------------------------- 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1404.926 ; gain = 322.039 ; free physical = 7426 ; free virtual = 42430 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2063.926 ; gain = 44.668 ; free physical = 7425 ; free virtual = 42429 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 2.1 Fix Topology Constraints Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 7359 ; free virtual = 42365 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.914 ; gain = 49.656 ; free physical = 7357 ; free virtual = 42363 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 7334 ; free virtual = 42340 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 7277 ; free virtual = 42287 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7280 ; free virtual = 42293 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7276 ; free virtual = 42289 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7274 ; free virtual = 42287 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7272 ; free virtual = 42286 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7274 ; free virtual = 42288 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7279 ; free virtual = 42293 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 7254 ; free virtual = 42269 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 7252 ; free virtual = 42267 Phase 9 Depositing Routes Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 7232 ; free virtual = 42248 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 7217 ; free virtual = 42234 Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 7212 ; free virtual = 42229 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 7243 ; free virtual = 42261 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2121.758 ; gain = 134.516 ; free physical = 7237 ; free virtual = 42255 Writing XDEF routing. Writing placer database... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 7247 ; free virtual = 42268 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 7286 ; free virtual = 42310 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 7207 ; free virtual = 42212 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 7132 ; free virtual = 42141 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 7142 ; free virtual = 42156 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 7029 ; free virtual = 42043 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 7008 ; free virtual = 42023 Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 7009 ; free virtual = 41998 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6955 ; free virtual = 41944 Phase 3 Initial Routing WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6946 ; free virtual = 41935 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6947 ; free virtual = 41936 Phase 4 Rip-up And Reroute | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6945 ; free virtual = 41934 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6943 ; free virtual = 41932 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6953 ; free virtual = 41942 Phase 6 Post Hold Fix | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6955 ; free virtual = 41944 Phase 7 Route finalize Running DRC as a precondition to command write_bitstream Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6979 ; free virtual = 41968 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6960 ; free virtual = 41949 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6923 ; free virtual = 41912 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2178.992 ; gain = 94.586 ; free physical = 6965 ; free virtual = 41954 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 2217.781 ; gain = 165.391 ; free physical = 6965 ; free virtual = 41954 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 6340 ; free virtual = 41351 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 6314 ; free virtual = 41325 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6279 ; free virtual = 41291 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Loading data files... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 6237 ; free virtual = 41254 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6166 ; free virtual = 41185 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | Loading data files... +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6165 ; free virtual = 41184 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6163 ; free virtual = 41182 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6162 ; free virtual = 41181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6162 ; free virtual = 41181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6162 ; free virtual = 41181 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6161 ; free virtual = 41180 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 6160 ; free virtual = 41179 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 6160 ; free virtual = 41180 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.781 ; gain = 0.000 ; free physical = 6150 ; free virtual = 41143 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13189 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13201 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 5665 ; free virtual = 40661 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2454.871 ; gain = 342.105 ; free physical = 5596 ; free virtual = 40592 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:14 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Bitstream size: 4243411 bytes WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 6498 ; free virtual = 41494 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 6484 ; free virtual = 41480 touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Loading site data... Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.926 ; gain = 41.668 ; free physical = 6037 ; free virtual = 41033 Loading site data... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.914 ; gain = 47.656 ; free physical = 5965 ; free virtual = 40962 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2066.914 ; gain = 47.656 ; free physical = 5965 ; free virtual = 40962 Loading route data... Processing options... Creating bitmap... Loading site data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2076.969 ; gain = 57.711 ; free physical = 5741 ; free virtual = 40738 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. Loading route data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Processing options... Creating bitmap... Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.445 ; gain = 0.000 ; free physical = 5730 ; free virtual = 40727 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5716 ; free virtual = 40713 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5718 ; free virtual = 40714 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5717 ; free virtual = 40713 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5715 ; free virtual = 40712 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5715 ; free virtual = 40712 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5715 ; free virtual = 40711 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.488 ; gain = 514.531 ; free physical = 5697 ; free virtual = 40693 Phase 1.3 Build Placer Netlist Model Congestion Report Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.488 ; gain = 514.531 ; free physical = 5690 ; free virtual = 40686 No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 1.4 Constrain Clocks/Macros West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2078.969 ; gain = 59.711 ; free physical = 5688 ; free virtual = 40684 Phase 8 Verifying routed nets Verification completed successfully Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.488 ; gain = 514.531 ; free physical = 5688 ; free virtual = 40685 Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 5687 ; free virtual = 40683 Phase 9 Depositing Routes Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.488 ; gain = 514.531 ; free physical = 5684 ; free virtual = 40680 Phase 2 Final Placement Cleanup Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 5682 ; free virtual = 40679 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2080.969 ; gain = 61.711 ; free physical = 5716 ; free virtual = 40713 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2119.758 ; gain = 132.516 ; free physical = 5716 ; free virtual = 40713 Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.488 ; gain = 514.531 ; free physical = 5716 ; free virtual = 40712 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.488 ; gain = 514.531 ; free physical = 5708 ; free virtual = 40704 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1986.488 ; gain = 581.562 ; free physical = 5708 ; free virtual = 40704 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2119.758 ; gain = 0.000 ; free physical = 5698 ; free virtual = 40697 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Creating bitstream... Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 5687 ; free virtual = 40692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 5694 ; free virtual = 40699 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1567] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1651] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1875] Parameter DOA_REG bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1903] Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1931] Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1959] Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1987] Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2015] Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2043] Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2071] Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2099] Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2127] Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2155] Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2183] Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2211] Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2239] Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2267] Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2295] Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2323] Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2351] Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2379] Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2407] Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2435] Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2463] Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2491] Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2519] Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2547] Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] Parameter SRVAL_B bound to: 18'b000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:16] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] Loading site data... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 5790 ; free virtual = 40797 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 5790 ; free virtual = 40796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 5775 ; free virtual = 40790 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 5783 ; free virtual = 40793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 5785 ; free virtual = 40795 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 5787 ; free virtual = 40797 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading route data... INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:17 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 5848 ; free virtual = 40858 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2532.898 ; gain = 339.105 ; free physical = 6030 ; free virtual = 41040 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:30 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 6020 ; free virtual = 41029 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2470.160 ; gain = 339.105 ; free physical = 6970 ; free virtual = 41979 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:32 2019... touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2461.863 ; gain = 340.105 ; free physical = 7772 ; free virtual = 42784 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:34 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 8550 ; free virtual = 43569 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 8522 ; free virtual = 43540 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 8516 ; free virtual = 43534 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:42 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:49 . Memory (MB): peak = 2608.945 ; gain = 391.160 ; free physical = 8316 ; free virtual = 43335 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:42 2019... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:28 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 8288 ; free virtual = 43305 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 8321 ; free virtual = 43337 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9003 ; free virtual = 44019 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9329 ; free virtual = 44346 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9325 ; free virtual = 44343 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9325 ; free virtual = 44342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9324 ; free virtual = 44341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9324 ; free virtual = 44341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9324 ; free virtual = 44341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9323 ; free virtual = 44340 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 9321 ; free virtual = 44338 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 9322 ; free virtual = 44339 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 9311 ; free virtual = 44328 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_005/OK Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9313 ; free virtual = 44331 Phase 1.3 Build Placer Netlist Model GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:29 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9315 ; free virtual = 44333 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9311 ; free virtual = 44329 Creating bitstream... Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9308 ; free virtual = 44326 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9294 ; free virtual = 44312 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:30 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 9285 ; free virtual = 44303 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 9283 ; free virtual = 44300 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9269 ; free virtual = 44287 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9267 ; free virtual = 44285 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9264 ; free virtual = 44282 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9267 ; free virtual = 44285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9266 ; free virtual = 44285 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9265 ; free virtual = 44283 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9268 ; free virtual = 44286 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 9264 ; free virtual = 44282 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:32 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 9265 ; free virtual = 44284 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13750 Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 9422 ; free virtual = 44444 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 9184 ; free virtual = 44207 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 9172 ; free virtual = 44194 Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:40 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 9284 ; free virtual = 44307 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 9472 ; free virtual = 44498 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14eeb77a5 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 9473 ; free virtual = 44500 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:53 . Memory (MB): peak = 2606.941 ; gain = 389.160 ; free physical = 9476 ; free virtual = 44503 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:54 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2460.863 ; gain = 341.105 ; free physical = 10713 ; free virtual = 45744 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:56 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 11533 ; free virtual = 46564 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:53:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:06 ; elapsed = 00:00:52 . Memory (MB): peak = 2607.902 ; gain = 390.121 ; free physical = 11333 ; free virtual = 46365 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:53:59 2019... WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11526 ; free virtual = 46557 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11813 ; free virtual = 46844 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11903 ; free virtual = 46934 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 13990 INFO: [Device 21-403] Loading part xc7z020clg400-1 Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 12556 ; free virtual = 47587 --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14023 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14120 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 11956 ; free virtual = 46993 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14165 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 12015 ; free virtual = 47052 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 12010 ; free virtual = 47047 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.434 ; gain = 60.824 ; free physical = 11920 ; free virtual = 46957 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11900 ; free virtual = 46937 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 11905 ; free virtual = 46942 --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11899 ; free virtual = 46936 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11898 ; free virtual = 46935 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11897 ; free virtual = 46934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11896 ; free virtual = 46933 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11895 ; free virtual = 46933 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11894 ; free virtual = 46932 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11891 ; free virtual = 46929 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 11892 ; free virtual = 46929 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-570] Preparing netlist for logic optimization Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 11502 ; free virtual = 46540 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 11375 ; free virtual = 46412 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 11376 ; free virtual = 46413 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 11351 ; free virtual = 46388 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 11341 ; free virtual = 46378 Phase 2 Final Placement Cleanup INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] Phase 2 Final Placement Cleanup | Checksum: bca60bcf WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 11336 ; free virtual = 46374 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] Parameter DOA_REG bound to: 0 - type: integer WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] Parameter DOB_REG bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 11335 ; free virtual = 46372 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:203] 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:229] place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 11335 ; free virtual = 46372 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:247] Command: route_design WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:286] Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2553] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2802] Running DRC as a precondition to command route_design WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3152] Command: report_drc (run_mandatory_drcs) for: router_checks WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3300] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 11148 ; free virtual = 46186 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 11174 ; free virtual = 46220 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 11182 ; free virtual = 46219 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.172 ; gain = 43.668 ; free physical = 11161 ; free virtual = 46207 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 11135 ; free virtual = 46173 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 11129 ; free virtual = 46167 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.160 ; gain = 49.656 ; free physical = 11121 ; free virtual = 46159 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.160 ; gain = 49.656 ; free physical = 11120 ; free virtual = 46158 Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Device 21-403] Loading part xc7z020clg400-1 Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 104554cdc Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10962 ; free virtual = 46000 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 10951 ; free virtual = 45989 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 117ddc37d Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2078.215 ; gain = 59.711 ; free physical = 10930 ; free virtual = 45968 --------------------------------------------------------------------------------- Phase 3 Initial Routing Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10937 ; free virtual = 45975 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10931 ; free virtual = 45969 Phase 1 Placer Initialization | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 10921 ; free virtual = 45959 Phase 2 Global Placement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10834 ; free virtual = 45872 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10816 ; free virtual = 45854 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10818 ; free virtual = 45856 Phase 5 Delay and Skew Optimization WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10821 ; free virtual = 45859 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10824 ; free virtual = 45862 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10828 ; free virtual = 45865 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 7 Route finalize 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 10839 ; free virtual = 45877 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 10885 ; free virtual = 45923 Phase 8 Verifying routed nets Verification completed successfully report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 10886 ; free virtual = 45924 Phase 9 Depositing Routes Command: report_drc (run_mandatory_drcs) for: placer_checks Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 10883 ; free virtual = 45921 INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.215 ; gain = 63.711 ; free physical = 10921 ; free virtual = 45959 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2121.004 ; gain = 134.516 ; free physical = 10921 ; free virtual = 45959 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:16] Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2121.004 ; gain = 0.000 ; free physical = 10886 ; free virtual = 45927 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.941 ; gain = 132.332 ; free physical = 10812 ; free virtual = 45851 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10837 ; free virtual = 45876 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 10838 ; free virtual = 45877 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.941 ; gain = 132.332 ; free physical = 10841 ; free virtual = 45880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.969 ; gain = 140.359 ; free physical = 10839 ; free virtual = 45878 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14922 Phase 2 Global Placement | Checksum: 19390bb85 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10687 ; free virtual = 45726 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19390bb85 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10670 ; free virtual = 45709 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22760be29 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10662 ; free virtual = 45701 Phase 3.3 Area Swap Optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.3 Area Swap Optimization | Checksum: 2013b9bf4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10688 ; free virtual = 45727 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1caeffc59 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10687 ; free virtual = 45726 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10662 ; free virtual = 45701 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:16] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 3.5 Small Shape Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10606 ; free virtual = 45645 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10597 ; free virtual = 45636 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10619 ; free virtual = 45658 Phase 3 Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10607 ; free virtual = 45646 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10595 ; free virtual = 45634 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10606 ; free virtual = 45645 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10599 ; free virtual = 45638 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10595 ; free virtual = 45634 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21932cca2 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10590 ; free virtual = 45629 Ending Placer Task | Checksum: 1d105b369 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 10595 ; free virtual = 45634 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 10594 ; free virtual = 45633 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.961 ; gain = 172.352 ; free physical = 10595 ; free virtual = 45640 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10590 ; free virtual = 45629 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10472 ; free virtual = 45512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 10471 ; free virtual = 45511 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] INFO: Launching helper process for spawning children vivado processesWARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] INFO: Helper process launched with PID 15049 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10436 ; free virtual = 45476 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10418 ; free virtual = 45459 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10414 ; free virtual = 45454 --------------------------------------------------------------------------------- Checksum: PlaceDB: ec660a5f ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10360 ; free virtual = 45400 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.566 ; gain = 216.121 ; free physical = 10220 ; free virtual = 45260 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.566 ; gain = 216.121 ; free physical = 10160 ; free virtual = 45200 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 10150 ; free virtual = 45189 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 10038 ; free virtual = 45078 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 10003 ; free virtual = 45043 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 10002 ; free virtual = 45042 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 9997 ; free virtual = 45037 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 9996 ; free virtual = 45036 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 9995 ; free virtual = 45035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 9995 ; free virtual = 45035 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 9993 ; free virtual = 45033 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.551 ; gain = 225.105 ; free physical = 9990 ; free virtual = 45030 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.559 ; gain = 225.105 ; free physical = 9991 ; free virtual = 45031 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15099 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1344.547 ; gain = 248.938 ; free physical = 9856 ; free virtual = 44896 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.547 ; gain = 248.938 ; free physical = 9816 ; free virtual = 44856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9768 ; free virtual = 44808 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 9668 ; free virtual = 44708 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9666 ; free virtual = 44706 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9662 ; free virtual = 44702 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9655 ; free virtual = 44695 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9654 ; free virtual = 44694 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9652 ; free virtual = 44692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9652 ; free virtual = 44693 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9651 ; free virtual = 44692 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 9648 ; free virtual = 44692 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9648 ; free virtual = 44693 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 9536 ; free virtual = 44577 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 9457 ; free virtual = 44498 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.176 ; gain = 43.668 ; free physical = 9373 ; free virtual = 44413 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.164 ; gain = 49.656 ; free physical = 9343 ; free virtual = 44383 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.164 ; gain = 49.656 ; free physical = 9342 ; free virtual = 44382 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4047] INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9297 ; free virtual = 44337 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9285 ; free virtual = 44325 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 9287 ; free virtual = 44327 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2083.469 ; gain = 60.961 ; free physical = 9277 ; free virtual = 44317 Phase 3 Initial Routing Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9273 ; free virtual = 44313 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9262 ; free virtual = 44303 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9269 ; free virtual = 44318 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9267 ; free virtual = 44316 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9266 ; free virtual = 44315 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9266 ; free virtual = 44315 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9265 ; free virtual = 44314 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9264 ; free virtual = 44313 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9270 ; free virtual = 44311 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 9270 ; free virtual = 44310 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 9273 ; free virtual = 44314 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 9264 ; free virtual = 44304 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 9300 ; free virtual = 44341 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2127.258 ; gain = 136.766 ; free physical = 9298 ; free virtual = 44339 Writing placer database... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9262 ; free virtual = 44303 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9262 ; free virtual = 44303 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9260 ; free virtual = 44302 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9254 ; free virtual = 44295 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Writing XDEF routing. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9223 ; free virtual = 44266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9221 ; free virtual = 44263 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9215 ; free virtual = 44259 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9213 ; free virtual = 44256 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Writing XDEF routing logical nets. Writing XDEF routing special nets. Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9209 ; free virtual = 44253 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 9203 ; free virtual = 44247 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 9199 ; free virtual = 44243 Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 9199 ; free virtual = 44243 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9149 ; free virtual = 44193 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9151 ; free virtual = 44195 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9149 ; free virtual = 44193 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9170 ; free virtual = 44211 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9172 ; free virtual = 44213 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9174 ; free virtual = 44215 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. --------------------------------------------------------------------------------- synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1416.590 ; gain = 333.703 ; free physical = 9174 ; free virtual = 44215 --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9171 ; free virtual = 44212 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9170 ; free virtual = 44210 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9167 ; free virtual = 44208 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 9168 ; free virtual = 44208 Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Loading site data... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] Loading route data... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1077] Processing options... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1575] Creating bitmap... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement Running DRC as a precondition to command write_bitstream INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9043 ; free virtual = 44085 --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1483.621 ; gain = 0.000 ; free physical = 9013 ; free virtual = 44055 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1483.621 ; gain = 0.000 ; free physical = 8984 ; free virtual = 44034 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9005 ; free virtual = 44047 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9004 ; free virtual = 44046 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8933 ; free virtual = 43975 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8640 ; free virtual = 43681 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8520 ; free virtual = 43562 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8507 ; free virtual = 43549 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8502 ; free virtual = 43544 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8501 ; free virtual = 43543 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8500 ; free virtual = 43541 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 8498 ; free virtual = 43540 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8498 ; free virtual = 43539 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 8468 ; free virtual = 43510 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 8252 ; free virtual = 43293 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 1468.242 ; gain = 385.359 ; free physical = 8160 ; free virtual = 43202 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8133 ; free virtual = 43175 Creating bitstream... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 8124 ; free virtual = 43165 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8029 ; free virtual = 43071 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.691 ; gain = 216.238 ; free physical = 8044 ; free virtual = 43086 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 8033 ; free virtual = 43075 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1547.945 ; gain = 0.000 ; free physical = 8010 ; free virtual = 43052 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1547.945 ; gain = 0.000 ; free physical = 8000 ; free virtual = 43042 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7968 ; free virtual = 43010 No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7967 ; free virtual = 43009 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7967 ; free virtual = 43009 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 7967 ; free virtual = 43009 --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7967 ; free virtual = 43009 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7967 ; free virtual = 43009 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7966 ; free virtual = 43008 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7966 ; free virtual = 43008 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 7965 ; free virtual = 43007 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.223 ; free physical = 7966 ; free virtual = 43008 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 7929 ; free virtual = 42974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 7923 ; free virtual = 42968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 8255 ; free virtual = 43301 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8252 ; free virtual = 43297 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8250 ; free virtual = 43296 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8228 ; free virtual = 43273 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8227 ; free virtual = 43273 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8227 ; free virtual = 43273 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8226 ; free virtual = 43271 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8223 ; free virtual = 43269 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 8223 ; free virtual = 43269 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 8219 ; free virtual = 43265 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1543.949 ; gain = 0.000 ; free physical = 8067 ; free virtual = 43113 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1543.949 ; gain = 0.000 ; free physical = 8043 ; free virtual = 43089 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:54:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.109 ; gain = 340.105 ; free physical = 8003 ; free virtual = 43049 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:54:44 2019... INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 8717 ; free virtual = 43769 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 8570 ; free virtual = 43621 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 8573 ; free virtual = 43625 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 8591 ; free virtual = 43643 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 8509 ; free virtual = 43582 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8508 ; free virtual = 43562 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 8507 ; free virtual = 43561 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.109 ; gain = 0.000 ; free physical = 8388 ; free virtual = 43461 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.152 ; gain = 510.531 ; free physical = 8339 ; free virtual = 43412 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.152 ; gain = 510.531 ; free physical = 8333 ; free virtual = 43407 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.152 ; gain = 510.531 ; free physical = 8330 ; free virtual = 43404 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.152 ; gain = 510.531 ; free physical = 8326 ; free virtual = 43399 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.152 ; gain = 510.531 ; free physical = 8324 ; free virtual = 43397 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.152 ; gain = 510.531 ; free physical = 8344 ; free virtual = 43398 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8344 ; free virtual = 43398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.152 ; gain = 577.562 ; free physical = 8344 ; free virtual = 43398 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8344 ; free virtual = 43397 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2062.922 ; gain = 44.668 ; free physical = 8516 ; free virtual = 43574 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.910 ; gain = 50.656 ; free physical = 8432 ; free virtual = 43490 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.910 ; gain = 50.656 ; free physical = 8419 ; free virtual = 43477 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 8354 ; free virtual = 43412 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8342 ; free virtual = 43400 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8339 ; free virtual = 43397 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8338 ; free virtual = 43396 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8338 ; free virtual = 43396 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8338 ; free virtual = 43396 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8336 ; free virtual = 43394 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 8295 ; free virtual = 43353 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 8287 ; free virtual = 43344 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 8310 ; free virtual = 43368 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 8346 ; free virtual = 43404 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2120.754 ; gain = 134.516 ; free physical = 8345 ; free virtual = 43403 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2120.754 ; gain = 0.000 ; free physical = 8291 ; free virtual = 43351 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:54:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2462.434 ; gain = 335.176 ; free physical = 8241 ; free virtual = 43299 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:54:57 2019... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 8741 ; free virtual = 43800 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 8724 ; free virtual = 43783 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 8718 ; free virtual = 43776 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.434 ; gain = 0.000 ; free physical = 8721 ; free virtual = 43780 Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 8730 ; free virtual = 43788 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 8710 ; free virtual = 43768 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 8697 ; free virtual = 43756 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 8694 ; free virtual = 43754 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 8693 ; free virtual = 43756 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 8701 ; free virtual = 43765 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 8687 ; free virtual = 43751 Phase 1.3 Build Placer Netlist Model INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8376 ; free virtual = 43439 --------------------------------------------------------------------------------- Loading data files... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8385 ; free virtual = 43448 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8373 ; free virtual = 43437 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8329 ; free virtual = 43393 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 8329 ; free virtual = 43393 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 171fe028c Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8081 ; free virtual = 43145 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8068 ; free virtual = 43132 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8063 ; free virtual = 43127 Phase 4 Rip-up And Reroute | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8063 ; free virtual = 43126 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8062 ; free virtual = 43126 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8062 ; free virtual = 43125 Phase 6 Post Hold Fix | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8058 ; free virtual = 43121 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 8056 ; free virtual = 43120 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 7 Route finalize --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8043 ; free virtual = 43106 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8037 ; free virtual = 43101 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8037 ; free virtual = 43101 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.227 ; gain = 9.684 ; free physical = 8077 ; free virtual = 43140 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2141.016 ; gain = 48.473 ; free physical = 8078 ; free virtual = 43142 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1904.438 ; gain = 0.000 ; free physical = 8074 ; free virtual = 43137 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 8057 ; free virtual = 43123 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 8040 ; free virtual = 43106 Phase 1.4 Constrain Clocks/Macros INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 8010 ; free virtual = 43074 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 7974 ; free virtual = 43038 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7975 ; free virtual = 43039 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7984 ; free virtual = 43049 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Running DRC as a precondition to command write_bitstream --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7964 ; free virtual = 43028 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7960 ; free virtual = 43025 --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7954 ; free virtual = 43018 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7953 ; free virtual = 43017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7952 ; free virtual = 43016 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7947 ; free virtual = 43012 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 7948 ; free virtual = 43012 INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.152 ; gain = 459.203 ; free physical = 7906 ; free virtual = 42971 Phase 1.3 Build Placer Netlist Model WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7560 ; free virtual = 42625 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.234 ; gain = 0.000 ; free physical = 7510 ; free virtual = 42575 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 459.203 ; free physical = 7538 ; free virtual = 42602 Phase 1.4 Constrain Clocks/Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7516 ; free virtual = 42580 Phase 3.2 Commit Most Macros & LUTRAMs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 459.203 ; free physical = 7480 ; free virtual = 42544 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 7443 ; free virtual = 42507 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 7416 ; free virtual = 42480 Phase 1.4 Constrain Clocks/Macros Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.152 ; gain = 459.203 ; free physical = 7416 ; free virtual = 42480 Phase 2 Global Placement Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 7395 ; free virtual = 42459 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 7373 ; free virtual = 42437 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 7357 ; free virtual = 42422 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 7337 ; free virtual = 42401 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.277 ; gain = 577.562 ; free physical = 7330 ; free virtual = 42394 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7277 ; free virtual = 42341 Phase 3.3 Area Swap Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7200 ; free virtual = 42264 Phase 3.4 Pipeline Register Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 7195 ; free virtual = 42259 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7176 ; free virtual = 42240 Phase 3.5 Small Shape Detail Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7099 ; free virtual = 42164 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7097 ; free virtual = 42162 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7096 ; free virtual = 42161 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7096 ; free virtual = 42160 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7094 ; free virtual = 42159 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 510.531 ; free physical = 7134 ; free virtual = 42199 INFO: Launching helper process for spawning children vivado processes 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 7134 ; free virtual = 42198 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: Helper process launched with PID 16747 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading site data... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 6939 ; free virtual = 42003 Phase 3.6 Re-assign LUT pins INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 6978 ; free virtual = 42043 Phase 3.7 Pipeline Register Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 6968 ; free virtual = 42032 Loading route data... Phase 3 Detail Placement Processing options... Phase 3.1 Commit Multi Column Macros Creating bitmap... Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 6948 ; free virtual = 42012 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 6927 ; free virtual = 41991 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 6919 ; free virtual = 41983 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7359 ; free virtual = 42424 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7375 ; free virtual = 42439 Phase 4.2 Post Placement Cleanup Phase 3.3 Area Swap Optimization Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7372 ; free virtual = 42436 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7367 ; free virtual = 42431 Phase 4.4 Final Placement Cleanup Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7367 ; free virtual = 42431 Phase 3.4 Pipeline Register Optimization Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7353 ; free virtual = 42417 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7352 ; free virtual = 42417 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7383 ; free virtual = 42447 Phase 3.5 Small Shape Detail Placement Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.191 ; gain = 543.246 ; free physical = 7380 ; free virtual = 42445 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.191 ; gain = 622.949 ; free physical = 7380 ; free virtual = 42444 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7282 ; free virtual = 42347 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7262 ; free virtual = 42326 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7232 ; free virtual = 42297 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7227 ; free virtual = 42292 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7218 ; free virtual = 42283 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7190 ; free virtual = 42255 Phase 4.3 Placer Reporting Phase 1 Build RT Design | Checksum: 147c036e4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 7166 ; free virtual = 42230 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c036e4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 7109 ; free virtual = 42173 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c036e4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 7109 ; free virtual = 42173 Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7100 ; free virtual = 42165 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7084 ; free virtual = 42148 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7066 ; free virtual = 42131 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 161e7cd46 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7096 ; free virtual = 42160 Phase 3 Initial Routing Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.195 ; gain = 547.246 ; free physical = 7083 ; free virtual = 42147 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.195 ; gain = 623.949 ; free physical = 7083 ; free virtual = 42147 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7067 ; free virtual = 42131 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7061 ; free virtual = 42126 Phase 4 Rip-up And Reroute | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7061 ; free virtual = 42126 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7061 ; free virtual = 42125 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7061 ; free virtual = 42125 Phase 6 Post Hold Fix | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7060 ; free virtual = 42125 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7003 ; free virtual = 42067 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7000 ; free virtual = 42064 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6998 ; free virtual = 42063 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7029 ; free virtual = 42093 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 7028 ; free virtual = 42093 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 7005 ; free virtual = 42071 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 6874 ; free virtual = 41939 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17223 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:55:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2460.859 ; gain = 340.105 ; free physical = 6718 ; free virtual = 41787 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:55:33 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:15 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 7807 ; free virtual = 42881 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 7803 ; free virtual = 42876 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] Phase 1 Placer Initialization WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] Phase 1.1 Placer Initialization Netlist Sorting WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1728] Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1542.859 ; gain = 0.000 ; free physical = 7721 ; free virtual = 42795 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1542.859 ; gain = 0.000 ; free physical = 7719 ; free virtual = 42793 Phase 1 Build RT Design | Checksum: 18a962264 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2068.836 ; gain = 42.668 ; free physical = 7694 ; free virtual = 42768 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18a962264 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.824 ; gain = 49.656 ; free physical = 7658 ; free virtual = 42732 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18a962264 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2075.824 ; gain = 49.656 ; free physical = 7657 ; free virtual = 42731 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:55:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2475.121 ; gain = 334.105 ; free physical = 7619 ; free virtual = 42692 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:55:40 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.129 ; gain = 61.961 ; free physical = 7621 ; free virtual = 42695 Phase 3 Initial Routing Loading site data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10fb680fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8103 ; free virtual = 43177 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8294 ; free virtual = 43367 Phase 4 Rip-up And Reroute | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8538 ; free virtual = 43612 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8566 ; free virtual = 43639 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8568 ; free virtual = 43642 Phase 6 Post Hold Fix | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8567 ; free virtual = 43640 Phase 7 Route finalize Bitstream size: 4243411 bytes Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Config size: 1060815 words Number of configuration frames: 9996 DONE Loading route data... Processing options... Creating bitmap... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.129 ; gain = 62.961 ; free physical = 8540 ; free virtual = 43614 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.129 ; gain = 65.961 ; free physical = 8531 ; free virtual = 43605 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10fb680fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.129 ; gain = 65.961 ; free physical = 8495 ; free virtual = 43569 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.129 ; gain = 65.961 ; free physical = 8540 ; free virtual = 43614 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.918 ; gain = 136.766 ; free physical = 8539 ; free virtual = 43613 touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2130.918 ; gain = 0.000 ; free physical = 8513 ; free virtual = 43591 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8498 ; free virtual = 43576 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8482 ; free virtual = 43558 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8482 ; free virtual = 43558 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.176 ; gain = 44.668 ; free physical = 8659 ; free virtual = 43740 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 8603 ; free virtual = 43684 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2073.164 ; gain = 50.656 ; free physical = 8602 ; free virtual = 43683 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2083.469 ; gain = 60.961 ; free physical = 8520 ; free virtual = 43601 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8501 ; free virtual = 43582 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8499 ; free virtual = 43580 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8498 ; free virtual = 43579 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8497 ; free virtual = 43578 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8497 ; free virtual = 43577 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.469 ; gain = 61.961 ; free physical = 8496 ; free virtual = 43577 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 8484 ; free virtual = 43564 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.469 ; gain = 64.961 ; free physical = 8482 ; free virtual = 43563 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 8464 ; free virtual = 43545 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 8502 ; free virtual = 43583 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2127.258 ; gain = 136.766 ; free physical = 8501 ; free virtual = 43582 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:55:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 8510 ; free virtual = 43591 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:55:50 2019... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Bitstream size: 4243411 bytes Config size: 1060815 words Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.65 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 9431 ; free virtual = 44515 Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 1352.070 ; gain = 256.152 ; free physical = 9371 ; free virtual = 44453 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9387 ; free virtual = 44470 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 1360.102 ; gain = 264.184 ; free physical = 9366 ; free virtual = 44469 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 9257 ; free virtual = 44340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 9251 ; free virtual = 44334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:42 . Memory (MB): peak = 1360.102 ; gain = 264.184 ; free physical = 9243 ; free virtual = 44326 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 9125 ; free virtual = 44208 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... Loading site data... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8924 ; free virtual = 44007 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8910 ; free virtual = 43993 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading route data... Processing options... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitmap... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8836 ; free virtual = 43920 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8811 ; free virtual = 43894 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8750 ; free virtual = 43834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8713 ; free virtual = 43797 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8711 ; free virtual = 43794 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 8724 ; free virtual = 43808 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1368.086 ; gain = 272.160 ; free physical = 8727 ; free virtual = 43810 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17585 INFO: [Project 1-571] Translating synthesized netlist Phase 1 Build RT Design | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2066.961 ; gain = 40.668 ; free physical = 8432 ; free virtual = 43515 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.949 ; gain = 48.656 ; free physical = 8387 ; free virtual = 43471 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a1f8442e Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.949 ; gain = 48.656 ; free physical = 8386 ; free virtual = 43470 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 8402 ; free virtual = 43485 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Build RT Design | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 8385 ; free virtual = 43468 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2075.945 ; gain = 50.656 ; free physical = 8351 ; free virtual = 43434 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2075.945 ; gain = 50.656 ; free physical = 8350 ; free virtual = 43434 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8334 ; free virtual = 43417 Phase 3 Initial Routing Number of Nodes with overlaps = 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Initial Routing | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8316 ; free virtual = 43399 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8305 ; free virtual = 43389 Phase 4 Rip-up And Reroute | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8302 ; free virtual = 43385 Phase 5 Delay and Skew Optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18932909f Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 8300 ; free virtual = 43384 Phase 3 Initial Routing Phase 5 Delay and Skew Optimization | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8301 ; free virtual = 43384 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8301 ; free virtual = 43384 Phase 6 Post Hold Fix | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8300 ; free virtual = 43383 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 8293 ; free virtual = 43376 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.379 ; gain = 61.086 ; free physical = 8301 ; free virtual = 43384 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 8298 ; free virtual = 43382 Phase 9 Depositing Routes Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 9 Depositing Routes | Checksum: 10276a5af Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 8283 ; free virtual = 43367 Number of Nodes with overlaps = 0 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 8321 ; free virtual = 43404 Routing Is Done. Phase 3 Initial Routing | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8321 ; free virtual = 43404 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2129.168 ; gain = 134.891 ; free physical = 8321 ; free virtual = 43404 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8316 ; free virtual = 43399 Phase 4 Rip-up And Reroute | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8311 ; free virtual = 43394 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8310 ; free virtual = 43393 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8308 ; free virtual = 43392 Phase 6 Post Hold Fix | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8308 ; free virtual = 43392 Writing placer database... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 8294 ; free virtual = 43378 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2092.250 ; gain = 66.961 ; free physical = 8294 ; free virtual = 43378 Phase 9 Depositing Routes Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 9 Depositing Routes | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.250 ; gain = 67.961 ; free physical = 8290 ; free virtual = 43376 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2093.250 ; gain = 67.961 ; free physical = 8327 ; free virtual = 43413 Routing Is Done. Write XDEF Complete: Time (s): cpu = 00:00:00.90 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2129.168 ; gain = 0.000 ; free physical = 8327 ; free virtual = 43414 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2132.039 ; gain = 138.766 ; free physical = 8327 ; free virtual = 43414 Writing placer database... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2132.039 ; gain = 0.000 ; free physical = 8367 ; free virtual = 43454 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.391 ; gain = 509.531 ; free physical = 8333 ; free virtual = 43417 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 8286 ; free virtual = 43371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 8254 ; free virtual = 43339 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17695 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8185 ; free virtual = 43269 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2129.422 ; gain = 38.230 ; free physical = 8191 ; free virtual = 43276 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.410 ; gain = 45.219 ; free physical = 8116 ; free virtual = 43201 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.410 ; gain = 45.219 ; free physical = 8115 ; free virtual = 43200 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 8065 ; free virtual = 43150 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7925 ; free virtual = 43010 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7879 ; free virtual = 42964 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7877 ; free virtual = 42961 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7875 ; free virtual = 42960 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7874 ; free virtual = 42959 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7873 ; free virtual = 42958 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading site data... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7850 ; free virtual = 42935 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7849 ; free virtual = 42933 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7847 ; free virtual = 42932 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.465 ; gain = 65.273 ; free physical = 7882 ; free virtual = 42966 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:51 . Memory (MB): peak = 2195.254 ; gain = 104.062 ; free physical = 7881 ; free virtual = 42966 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7953 ; free virtual = 43039 --------------------------------------------------------------------------------- Writing placer database... Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7920 ; free virtual = 43007 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7862 ; free virtual = 42950 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7848 ; free virtual = 42937 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7864 ; free virtual = 42953 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7861 ; free virtual = 42951 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7860 ; free virtual = 42950 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 7873 ; free virtual = 42963 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 7882 ; free virtual = 42973 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-571] Translating synthesized netlist Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2130.426 ; gain = 39.230 ; free physical = 7832 ; free virtual = 42924 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 509.531 ; free physical = 7791 ; free virtual = 42885 Phase 1.4 Constrain Clocks/Macros Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2137.414 ; gain = 46.219 ; free physical = 7791 ; free virtual = 42884 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2137.414 ; gain = 46.219 ; free physical = 7791 ; free virtual = 42884 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 509.531 ; free physical = 7767 ; free virtual = 42861 Loading data files... Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 509.531 ; free physical = 7747 ; free virtual = 42843 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 7740 ; free virtual = 42836 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 509.531 ; free physical = 7716 ; free virtual = 42813 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 7721 ; free virtual = 42821 Phase 3 Initial Routing Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.391 ; gain = 509.531 ; free physical = 7920 ; free virtual = 43022 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 7957 ; free virtual = 43060 place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 7957 ; free virtual = 43060 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 7998 ; free virtual = 43101 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8000 ; free virtual = 43102 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8007 ; free virtual = 43109 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8029 ; free virtual = 43131 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8030 ; free virtual = 43132 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. INFO: [Vivado 12-1842] Bitgen Completed Successfully. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8067 ; free virtual = 43170 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8066 ; free virtual = 43169 Phase 9 Depositing Routes INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8063 ; free virtual = 43166 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 64.273 ; free physical = 8094 ; free virtual = 43198 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2194.258 ; gain = 103.062 ; free physical = 8093 ; free virtual = 43196 Writing placer database... Creating bitstream... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2195.254 ; gain = 0.000 ; free physical = 7924 ; free virtual = 43042 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 7947 ; free virtual = 43070 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 7961 ; free virtual = 43062 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 7961 ; free virtual = 43062 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 7950 ; free virtual = 43052 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.258 ; gain = 0.000 ; free physical = 7667 ; free virtual = 42782 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:56:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2469.023 ; gain = 338.105 ; free physical = 7808 ; free virtual = 42925 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:56:15 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 8364 ; free virtual = 43459 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 17850 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 9062 ; free virtual = 44165 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 9050 ; free virtual = 44153 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 9047 ; free virtual = 44150 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:56:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2461.434 ; gain = 334.176 ; free physical = 8976 ; free virtual = 44079 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:56:18 2019... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 8971 ; free virtual = 44074 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Loading route data... Processing options... Creating bitmap... Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9332 ; free virtual = 44435 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 9281 ; free virtual = 44385 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9268 ; free virtual = 44371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Loading data files... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9168 ; free virtual = 44271 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9168 ; free virtual = 44271 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9166 ; free virtual = 44270 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9166 ; free virtual = 44270 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9206 ; free virtual = 44309 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9206 ; free virtual = 44310 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9206 ; free virtual = 44310 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 9196 ; free virtual = 44299 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 9197 ; free virtual = 44301 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:16 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 9143 ; free virtual = 44246 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 8919 ; free virtual = 44022 --------------------------------------------------------------------------------- Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 8927 ; free virtual = 44030 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8925 ; free virtual = 44028 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 8930 ; free virtual = 44033 --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1543.859 ; gain = 0.000 ; free physical = 8916 ; free virtual = 44019 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.66 . Memory (MB): peak = 1543.859 ; gain = 0.000 ; free physical = 8904 ; free virtual = 44008 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8844 ; free virtual = 43948 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8842 ; free virtual = 43945 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8840 ; free virtual = 43943 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8839 ; free virtual = 43942 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8837 ; free virtual = 43941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8837 ; free virtual = 43940 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8835 ; free virtual = 43938 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 8834 ; free virtual = 43937 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 8834 ; free virtual = 43937 INFO: [Project 1-571] Translating synthesized netlist Loading site data... Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8780 ; free virtual = 43888 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 8980 ; free virtual = 44088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 8990 ; free virtual = 44097 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9013 ; free virtual = 44121 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Creating bitstream... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:36 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 8980 ; free virtual = 44088 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 8830 ; free virtual = 43938 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 8821 ; free virtual = 43928 Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing bitstream ./design.bit... INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:13 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 8887 ; free virtual = 43999 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:56:36 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [DRC 23-27] Running DRC with 8 threads 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:34 . Memory (MB): peak = 2467.273 ; gain = 338.105 ; free physical = 9019 ; free virtual = 44131 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:56:37 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 9342 ; free virtual = 44453 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Bitstream size: 4243411 bytes Config size: 1060815 words Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 10211 ; free virtual = 45328 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 165c53615 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 10209 ; free virtual = 45327 Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1550.863 ; gain = 0.000 ; free physical = 10235 ; free virtual = 45352 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.39 . Memory (MB): peak = 1550.863 ; gain = 0.000 ; free physical = 10245 ; free virtual = 45362 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 10177 ; free virtual = 45294 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 10173 ; free virtual = 45290 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 10170 ; free virtual = 45287 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:56:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2470.145 ; gain = 338.105 ; free physical = 10182 ; free virtual = 45300 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:56:41 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:56:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2533.320 ; gain = 338.066 ; free physical = 11127 ; free virtual = 46245 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:56:41 2019... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11147 ; free virtual = 46266 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11149 ; free virtual = 46268 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11154 ; free virtual = 46273 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11156 ; free virtual = 46275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11159 ; free virtual = 46278 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11161 ; free virtual = 46281 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11165 ; free virtual = 46285 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 11172 ; free virtual = 46293 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 11175 ; free virtual = 46295 INFO: [Project 1-571] Translating synthesized netlist touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18298 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18338 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 12175 ; free virtual = 47299 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:56:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2533.363 ; gain = 339.105 ; free physical = 12184 ; free virtual = 47308 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:56:45 2019... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 13084 ; free virtual = 48208 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 13084 ; free virtual = 48208 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 12784 ; free virtual = 47913 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.391 ; gain = 508.531 ; free physical = 12625 ; free virtual = 47754 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 12558 ; free virtual = 47687 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 12217 ; free virtual = 47346 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 12091 ; free virtual = 47220 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 12081 ; free virtual = 47210 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 12076 ; free virtual = 47205 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 12073 ; free virtual = 47203 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 12073 ; free virtual = 47202 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 515.531 ; free physical = 12072 ; free virtual = 47201 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 12072 ; free virtual = 47201 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 12124 ; free virtual = 47254 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2136.074 ; gain = 51.668 ; free physical = 11877 ; free virtual = 47006 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] Phase 2.1 Fix Topology Constraints | Checksum: 130471fa6 WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 11779 ; free virtual = 46908 Phase 2.2 Pre Route Cleanup WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] Phase 2.2 Pre Route Cleanup | Checksum: 130471fa6 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 11768 ; free virtual = 46898 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 508.531 ; free physical = 11688 ; free virtual = 46818 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 508.531 ; free physical = 11636 ; free virtual = 46766 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11584 ; free virtual = 46713 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 11502 ; free virtual = 46631 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11498 ; free virtual = 46627 Phase 1 Placer Initialization | Checksum: 208e4f915 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 508.531 ; free physical = 11493 ; free virtual = 46622 Phase 2 Final Placement Cleanup ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 11438 ; free virtual = 46568 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 508.531 ; free physical = 11383 ; free virtual = 46512 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 11380 ; free virtual = 46509 Number of Nodes with overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Router Initialization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11398 ; free virtual = 46527 Phase 3 Initial Routing Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 508.531 ; free physical = 11363 ; free virtual = 46493 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 11359 ; free virtual = 46489 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11288 ; free virtual = 46418 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11263 ; free virtual = 46393 Phase 4 Rip-up And Reroute | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11260 ; free virtual = 46389 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11257 ; free virtual = 46387 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11254 ; free virtual = 46384 Phase 6 Post Hold Fix | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11252 ; free virtual = 46381 Phase 7 Route finalize WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e0a71f46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 11227 ; free virtual = 46357 Phase 1.3 Build Placer Netlist Model Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 1.3 Build Placer Netlist Model | Checksum: 277f9852c West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 11218 ; free virtual = 46347 Phase 1.4 Constrain Clocks/Macros Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 7 Route finalize | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11214 ; free virtual = 46344 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11206 ; free virtual = 46336 Phase 9 Depositing Routes Phase 1.4 Constrain Clocks/Macros | Checksum: 277f9852c Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 11205 ; free virtual = 46335 Phase 1 Placer Initialization | Checksum: 277f9852c Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 11201 ; free virtual = 46330 Phase 2 Global Placement INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11201 ; free virtual = 46330 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 11240 ; free virtual = 46369 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:48 . Memory (MB): peak = 2218.781 ; gain = 166.391 ; free physical = 11237 ; free virtual = 46367 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 18712 Writing placer database... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 11260 ; free virtual = 46391 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.395 ; gain = 501.531 ; free physical = 10940 ; free virtual = 46088 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10957 ; free virtual = 46108 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10952 ; free virtual = 46103 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2433660c9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10948 ; free virtual = 46099 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d113e94 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10941 ; free virtual = 46094 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6c59ef9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10940 ; free virtual = 46093 Phase 3.5 Small Shape Detail Placement Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.781 ; gain = 0.000 ; free physical = 10881 ; free virtual = 46039 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19304 Phase 3.5 Small Shape Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10864 ; free virtual = 46023 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10862 ; free virtual = 46021 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10859 ; free virtual = 46017 Phase 3 Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10856 ; free virtual = 46015 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10853 ; free virtual = 46012 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10836 ; free virtual = 45994 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10828 ; free virtual = 45986 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10821 ; free virtual = 45979 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10816 ; free virtual = 45975 Ending Placer Task | Checksum: 1d0f627a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.551 ; gain = 603.578 ; free physical = 10843 ; free virtual = 46002 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.551 ; gain = 667.609 ; free physical = 10843 ; free virtual = 46002 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19347 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.781 ; gain = 0.000 ; free physical = 10778 ; free virtual = 45911 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec567e97 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 10622 ; free virtual = 45755 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 10592 ; free virtual = 45724 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10547 ; free virtual = 45680 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 501.531 ; free physical = 10342 ; free virtual = 45475 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 501.531 ; free physical = 10317 ; free virtual = 45450 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 501.531 ; free physical = 10319 ; free virtual = 45451 Phase 2 Final Placement Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 10320 ; free virtual = 45453 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 501.531 ; free physical = 10281 ; free virtual = 45414 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10290 ; free virtual = 45423 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10293 ; free virtual = 45425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10287 ; free virtual = 45419 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10286 ; free virtual = 45419 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10285 ; free virtual = 45418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10285 ; free virtual = 45418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10285 ; free virtual = 45418 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10278 ; free virtual = 45411 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 10279 ; free virtual = 45411 Ending Placer Task | Checksum: 110ed1b10 INFO: [Project 1-571] Translating synthesized netlist Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.395 ; gain = 501.531 ; free physical = 10264 ; free virtual = 45397 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 10242 ; free virtual = 45375 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10155 ; free virtual = 45288 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10136 ; free virtual = 45269 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10136 ; free virtual = 45268 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10135 ; free virtual = 45267 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10133 ; free virtual = 45266 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 10134 ; free virtual = 45266 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 10133 ; free virtual = 45266 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10121 ; free virtual = 45267 --------------------------------------------------------------------------------- Starting Routing Task INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 10092 ; free virtual = 45226 --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19466 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9988 ; free virtual = 45143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9988 ; free virtual = 45123 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9987 ; free virtual = 45122 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9973 ; free virtual = 45108 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9971 ; free virtual = 45106 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9958 ; free virtual = 45093 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.434 ; gain = 55.992 ; free physical = 9752 ; free virtual = 44887 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9651 ; free virtual = 44786 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 9653 ; free virtual = 44789 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 9504 ; free virtual = 44639 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 9493 ; free virtual = 44628 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] Loading data files... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 9482 ; free virtual = 44618 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.941 ; gain = 116.500 ; free physical = 9485 ; free virtual = 44621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 9485 ; free virtual = 44621 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.969 ; gain = 124.527 ; free physical = 9339 ; free virtual = 44475 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 9144 ; free virtual = 44280 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:7] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 8966 ; free virtual = 44106 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 8964 ; free virtual = 44106 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8961 ; free virtual = 44102 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8965 ; free virtual = 44101 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8937 ; free virtual = 44080 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 8937 ; free virtual = 44079 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 8847 ; free virtual = 43990 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8846 ; free virtual = 43988 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 8846 ; free virtual = 43989 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8841 ; free virtual = 43984 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8839 ; free virtual = 43982 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8839 ; free virtual = 43981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8838 ; free virtual = 43981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8838 ; free virtual = 43981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8837 ; free virtual = 43979 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 8835 ; free virtual = 43978 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 8836 ; free virtual = 43978 INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 8798 ; free virtual = 43941 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8669 ; free virtual = 43805 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 8612 ; free virtual = 43748 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1656] Loading route data... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.680 ; gain = 215.238 ; free physical = 8575 ; free virtual = 43711 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.680 ; gain = 215.238 ; free physical = 8555 ; free virtual = 43691 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8553 ; free virtual = 43689 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8552 ; free virtual = 43688 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8550 ; free virtual = 43686 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8544 ; free virtual = 43681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8543 ; free virtual = 43679 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8543 ; free virtual = 43679 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8542 ; free virtual = 43678 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8542 ; free virtual = 43678 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 8541 ; free virtual = 43677 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8542 ; free virtual = 43679 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8515 ; free virtual = 43651 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8513 ; free virtual = 43650 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8509 ; free virtual = 43645 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8509 ; free virtual = 43645 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8507 ; free virtual = 43644 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8507 ; free virtual = 43644 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8507 ; free virtual = 43644 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.672 ; gain = 225.230 ; free physical = 8504 ; free virtual = 43640 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 8505 ; free virtual = 43641 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 8365 ; free virtual = 43502 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 8314 ; free virtual = 43450 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 8313 ; free virtual = 43449 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8286 ; free virtual = 43423 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8285 ; free virtual = 43421 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8301 ; free virtual = 43437 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8189 ; free virtual = 43325 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8182 ; free virtual = 43318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8139 ; free virtual = 43275 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8138 ; free virtual = 43274 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8165 ; free virtual = 43301 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8167 ; free virtual = 43304 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8167 ; free virtual = 43304 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8165 ; free virtual = 43301 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 8164 ; free virtual = 43301 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Creating bitstream... 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 1416.711 ; gain = 333.828 ; free physical = 8128 ; free virtual = 43265 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7873 ; free virtual = 43009 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 7859 ; free virtual = 42995 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 7842 ; free virtual = 42978 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 7809 ; free virtual = 42945 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 7801 ; free virtual = 42938 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 7791 ; free virtual = 42927 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 7786 ; free virtual = 42922 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 7785 ; free virtual = 42921 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 7784 ; free virtual = 42920 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 7783 ; free virtual = 42920 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8005 ; free virtual = 43147 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2063.926 ; gain = 45.668 ; free physical = 8037 ; free virtual = 43198 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 8004 ; free virtual = 43166 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 8004 ; free virtual = 43166 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2078.969 ; gain = 60.711 ; free physical = 7951 ; free virtual = 43112 Phase 3 Initial Routing Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 7901 ; free virtual = 43043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7901 ; free virtual = 43043 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 7901 ; free virtual = 43043 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7902 ; free virtual = 43044 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7902 ; free virtual = 43044 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7901 ; free virtual = 43043 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7902 ; free virtual = 43044 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7902 ; free virtual = 43044 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Device 21-403] Loading part xc7z020clg400-1 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 7901 ; free virtual = 43043 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 7900 ; free virtual = 43043 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 7897 ; free virtual = 43039 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 7932 ; free virtual = 43075 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2121.758 ; gain = 135.516 ; free physical = 7932 ; free virtual = 43074 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 7911 ; free virtual = 43055 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:57:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:42 . Memory (MB): peak = 2608.941 ; gain = 390.160 ; free physical = 7921 ; free virtual = 43066 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:57:46 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 1 Build RT Design | Checksum: 10fbb77b1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 8927 ; free virtual = 44068 DONE Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10fbb77b1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 8892 ; free virtual = 44034 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10fbb77b1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.551 ; gain = 0.000 ; free physical = 8895 ; free virtual = 44037 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174384e93 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8889 ; free virtual = 44032 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8836 ; free virtual = 43978 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8831 ; free virtual = 43974 Phase 4 Rip-up And Reroute | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8831 ; free virtual = 43973 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8835 ; free virtual = 43977 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8835 ; free virtual = 43977 Phase 6 Post Hold Fix | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8835 ; free virtual = 43977 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8824 ; free virtual = 43966 Phase 8 Verifying routed nets Verification completed successfully INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 8 Verifying routed nets | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8820 ; free virtual = 43962 Phase 9 Depositing Routes Phase 1 Build RT Design | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 8828 ; free virtual = 43971 Phase 9 Depositing Routes | Checksum: 706f0e10 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8835 ; free virtual = 43978 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2102.234 ; gain = 9.684 ; free physical = 8881 ; free virtual = 44024 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2141.023 ; gain = 48.473 ; free physical = 8887 ; free virtual = 44029 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:46 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 8898 ; free virtual = 44040 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing placer database... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2141.023 ; gain = 0.000 ; free physical = 8942 ; free virtual = 44092 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2.1 Fix Topology Constraints | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 8910 ; free virtual = 44060 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10072c28e Time (s): cpu = 00:00:42 ; elapsed = 00:00:50 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 8911 ; free virtual = 44062 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8886 ; free virtual = 44034 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks Starting Placer Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 8810 ; free virtual = 43958 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8764 ; free virtual = 43912 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8746 ; free virtual = 43894 Phase 4 Rip-up And Reroute | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8746 ; free virtual = 43894 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8743 ; free virtual = 43891 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8741 ; free virtual = 43889 Phase 6 Post Hold Fix | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8740 ; free virtual = 43888 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.90 . Memory (MB): peak = 1548.949 ; gain = 0.000 ; free physical = 8741 ; free virtual = 43889 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8714 ; free virtual = 43862 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8709 ; free virtual = 43857 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8707 ; free virtual = 43855 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 9 Depositing Routes | Checksum: 1a3bb806c Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8724 ; free virtual = 43872 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:53 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 8765 ; free virtual = 43914 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2219.781 ; gain = 167.391 ; free physical = 8765 ; free virtual = 43913 Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:13 . Memory (MB): peak = 1476.832 ; gain = 393.945 ; free physical = 8394 ; free virtual = 43557 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing XDEF routing. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 8074 ; free virtual = 43247 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 8071 ; free virtual = 43245 --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.781 ; gain = 0.000 ; free physical = 8065 ; free virtual = 43241 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 1344.102 ; gain = 248.184 ; free physical = 8063 ; free virtual = 43241 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8061 ; free virtual = 43238 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8074 ; free virtual = 43251 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8068 ; free virtual = 43245 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8046 ; free virtual = 43223 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8041 ; free virtual = 43218 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Starting Placer Task Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 8036 ; free virtual = 43214 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 8036 ; free virtual = 43214 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Phase 1 Build RT Design | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 8019 ; free virtual = 43197 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.863 ; gain = 0.000 ; free physical = 8019 ; free virtual = 43197 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 7988 ; free virtual = 43157 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 7995 ; free virtual = 43157 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2219.781 ; gain = 0.000 ; free physical = 8003 ; free virtual = 43154 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.55 . Memory (MB): peak = 1558.863 ; gain = 0.000 ; free physical = 7996 ; free virtual = 43147 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1088853dc Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7912 ; free virtual = 43063 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7914 ; free virtual = 43066 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1 Build RT Design | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2135.078 ; gain = 50.668 ; free physical = 7912 ; free virtual = 43064 Phase 4.1 Global Iteration 0 | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7912 ; free virtual = 43063 Phase 4 Rip-up And Reroute | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7912 ; free virtual = 43063 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7912 ; free virtual = 43063 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7912 ; free virtual = 43063 Phase 6 Post Hold Fix | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7912 ; free virtual = 43063 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 7892 ; free virtual = 43044 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 7888 ; free virtual = 43040 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:47 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7887 ; free virtual = 43038 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 7882 ; free virtual = 43033 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 7911 ; free virtual = 43062 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2112.766 ; gain = 180.516 ; free physical = 7908 ; free virtual = 43059 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Writing placer database... Writing XDEF routing. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2112.766 ; gain = 0.000 ; free physical = 7913 ; free virtual = 43066 Starting Routing Task Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design.dcp' has been generated. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2.1 Fix Topology Constraints | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 7871 ; free virtual = 43022 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1cc0cc705 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 7855 ; free virtual = 43007 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7563 ; free virtual = 42715 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7487 ; free virtual = 42638 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7473 ; free virtual = 42624 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7484 ; free virtual = 42636 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7484 ; free virtual = 42636 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7483 ; free virtual = 42634 --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7483 ; free virtual = 42634 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Rip-up And Reroute | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7483 ; free virtual = 42635 Phase 5 Delay and Skew Optimization --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7483 ; free virtual = 42635 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7489 ; free virtual = 42640 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 7483 ; free virtual = 42635 Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7484 ; free virtual = 42636 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7482 ; free virtual = 42633 Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:50 . Memory (MB): peak = 1352.086 ; gain = 256.160 ; free physical = 7483 ; free virtual = 42634 Phase 5 Delay and Skew Optimization | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7485 ; free virtual = 42636 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Project 1-571] Translating synthesized netlist Phase 6.1 Hold Fix Iter | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7484 ; free virtual = 42636 Phase 6 Post Hold Fix | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7474 ; free virtual = 42625 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7462 ; free virtual = 42614 Phase 8 Verifying routed nets Verification completed successfully Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 7464 ; free virtual = 42615 Phase 1.3 Build Placer Netlist Model Phase 8 Verifying routed nets | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7464 ; free virtual = 42615 Phase 9 Depositing Routes Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 7454 ; free virtual = 42606 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 7451 ; free virtual = 42603 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 7449 ; free virtual = 42601 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 7446 ; free virtual = 42598 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 7439 ; free virtual = 42591 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 7439 ; free virtual = 42590 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 169be60b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7428 ; free virtual = 42580 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 7473 ; free virtual = 42624 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2216.785 ; gain = 164.391 ; free physical = 7472 ; free virtual = 42624 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Loading site data... Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2216.785 ; gain = 0.000 ; free physical = 6945 ; free virtual = 42124 Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2216.785 ; gain = 0.000 ; free physical = 6869 ; free virtual = 42023 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... Writing bitstream ./design.bit... INFO: Launching helper process for spawning children vivado processes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: Helper process launched with PID 20023 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 5867 ; free virtual = 41025 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 6023 ; free virtual = 41182 Phase 1.3 Build Placer Netlist Model WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:58:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2460.863 ; gain = 339.105 ; free physical = 6189 ; free virtual = 41352 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:58:21 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 21992 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 Loading data files... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 6867 ; free virtual = 42031 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 6809 ; free virtual = 41973 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 2003.152 ; gain = 454.203 ; free physical = 6790 ; free virtual = 41954 Phase 2 Global Placement INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading site data... Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 6693 ; free virtual = 41857 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:58:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing bitstream ./design.bit... 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2475.129 ; gain = 334.105 ; free physical = 6680 ; free virtual = 41845 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:58:24 2019... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Bitstream size: 4243411 bytes INFO: [Vivado 12-1842] Bitgen Completed Successfully. Config size: 1060815 words INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Number of configuration frames: 9996 DONE touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 22337 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7868 ; free virtual = 43038 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7846 ; free virtual = 43015 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7792 ; free virtual = 42962 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7796 ; free virtual = 42965 Phase 3.4 Pipeline Register Optimization Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 7796 ; free virtual = 42965 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7797 ; free virtual = 42967 Phase 1.3 Build Placer Netlist Model Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 7796 ; free virtual = 42966 Phase 3.5 Small Shape Detail Placement INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:58:29 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2454.871 ; gain = 342.105 ; free physical = 7773 ; free virtual = 42948 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:58:29 2019... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] Bitstream size: 4243411 bytes INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] Config size: 1060815 words WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] Number of configuration frames: 9996 WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] DONE WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2088] Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2136] Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8748 ; free virtual = 43922 Phase 3.6 Re-assign LUT pins WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8750 ; free virtual = 43925 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8710 ; free virtual = 43884 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8678 ; free virtual = 43853 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8644 ; free virtual = 43818 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4.2 Post Placement Cleanup INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8682 ; free virtual = 43857 Phase 4.3 Placer Reporting 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:21 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 8721 ; free virtual = 43896 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8719 ; free virtual = 43893 Phase 4.4 Final Placement Cleanup Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8700 ; free virtual = 43875 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8690 ; free virtual = 43865 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 550.250 ; free physical = 8669 ; free virtual = 43844 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.199 ; gain = 630.953 ; free physical = 8669 ; free virtual = 43843 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 8561 ; free virtual = 43736 Phase 1.4 Constrain Clocks/Macros Loading site data... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 8550 ; free virtual = 43725 Loading route data... Phase 1 Placer Initialization | Checksum: 208e4f915 Processing options... Creating bitmap... Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 8520 ; free virtual = 43694 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 8555 ; free virtual = 43729 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 8593 ; free virtual = 43768 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 8583 ; free virtual = 43758 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 8583 ; free virtual = 43758 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 8580 ; free virtual = 43755 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 8581 ; free virtual = 43756 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1543.867 ; gain = 0.000 ; free physical = 8567 ; free virtual = 43741 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.50 . Memory (MB): peak = 1543.867 ; gain = 0.000 ; free physical = 8565 ; free virtual = 43739 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.469 ; gain = 59.961 ; free physical = 8554 ; free virtual = 43729 Phase 3 Initial Routing Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8522 ; free virtual = 43697 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8524 ; free virtual = 43699 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8524 ; free virtual = 43699 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8524 ; free virtual = 43699 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8524 ; free virtual = 43699 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 8524 ; free virtual = 43699 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 8530 ; free virtual = 43705 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 8530 ; free virtual = 43705 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 8529 ; free virtual = 43704 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 8567 ; free virtual = 43742 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 8567 ; free virtual = 43742 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 8547 ; free virtual = 43725 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Creating bitstream... Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:58:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:49 . Memory (MB): peak = 2605.902 ; gain = 386.121 ; free physical = 8443 ; free virtual = 43622 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:58:47 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21306 Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9439 ; free virtual = 44623 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 9541 ; free virtual = 44745 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:34 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9528 ; free virtual = 44713 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 9528 ; free virtual = 44713 Phase 2.2 Pre Route Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 9528 ; free virtual = 44713 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:34 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9522 ; free virtual = 44707 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2083.469 ; gain = 59.961 ; free physical = 9483 ; free virtual = 44669 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9452 ; free virtual = 44637 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9438 ; free virtual = 44624 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9438 ; free virtual = 44623 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9437 ; free virtual = 44623 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9436 ; free virtual = 44622 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9436 ; free virtual = 44621 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 9412 ; free virtual = 44597 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 9411 ; free virtual = 44596 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 9406 ; free virtual = 44591 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:54 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 9443 ; free virtual = 44629 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 9443 ; free virtual = 44629 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 9416 ; free virtual = 44604 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:58:54 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:45 . Memory (MB): peak = 2607.945 ; gain = 391.160 ; free physical = 9361 ; free virtual = 44547 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:58:54 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" Processing options... ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1412f7e16 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2066.957 ; gain = 40.668 ; free physical = 10143 ; free virtual = 45329 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1412f7e16 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2072.945 ; gain = 46.656 ; free physical = 10076 ; free virtual = 45262 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1412f7e16 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2072.945 ; gain = 46.656 ; free physical = 10088 ; free virtual = 45274 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:40 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 10117 ; free virtual = 45303 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.250 ; gain = 58.961 ; free physical = 10058 ; free virtual = 45244 Phase 3 Initial Routing INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21556 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9915 ; free virtual = 45101 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9914 ; free virtual = 45099 Phase 4 Rip-up And Reroute | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9907 ; free virtual = 45093 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9897 ; free virtual = 45083 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9867 ; free virtual = 45053 Phase 6 Post Hold Fix | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9861 ; free virtual = 45047 INFO: Launching helper process for spawning children vivado processes Phase 7 Route finalize INFO: Helper process launched with PID 21586 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 9824 ; free virtual = 45010 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 9810 ; free virtual = 44996 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 9809 ; free virtual = 44995 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:53 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 9845 ; free virtual = 45031 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:56 . Memory (MB): peak = 2129.039 ; gain = 134.766 ; free physical = 9845 ; free virtual = 45031 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... INFO: [Timing 38-35] Done setting XDC timing constraints. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Creating bitstream... Write XDEF Complete: Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2129.039 ; gain = 0.000 ; free physical = 9801 ; free virtual = 44990 Loading data files... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 9783 ; free virtual = 44970 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 9714 ; free virtual = 44900 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer Writing bitstream ./design.bit... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 9558 ; free virtual = 44745 --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 9660 ; free virtual = 44851 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 9859 ; free virtual = 45049 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:46 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9772 ; free virtual = 44962 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9690 ; free virtual = 44880 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:16] Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9669 ; free virtual = 44859 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:47 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9667 ; free virtual = 44857 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9666 ; free virtual = 44856 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9660 ; free virtual = 44851 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9656 ; free virtual = 44847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9655 ; free virtual = 44846 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 9655 ; free virtual = 44846 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:48 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9658 ; free virtual = 44848 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9632 ; free virtual = 44824 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:59:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2470.363 ; gain = 343.105 ; free physical = 9628 ; free virtual = 44825 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:59:06 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9656 ; free virtual = 44847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 9659 ; free virtual = 44850 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 10547 ; free virtual = 45738 Phase 1.4 Constrain Clocks/Macros touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_013 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 10492 ; free virtual = 45683 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 10493 ; free virtual = 45684 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 10470 ; free virtual = 45661 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 10441 ; free virtual = 45633 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.398 ; gain = 508.531 ; free physical = 10382 ; free virtual = 45573 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 10375 ; free virtual = 45566 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] Loading site data... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10312 ; free virtual = 45505 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 10272 ; free virtual = 45465 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10271 ; free virtual = 45464 --------------------------------------------------------------------------------- Loading route data... INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 10279 ; free virtual = 45472 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 10214 ; free virtual = 45407 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 10197 ; free virtual = 45390 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21780 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1968] Creating bitstream... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9659 ; free virtual = 44852 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Loading site data... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9644 ; free virtual = 44838 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9884 ; free virtual = 45081 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 9808 ; free virtual = 45005 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 9789 ; free virtual = 44987 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9786 ; free virtual = 44983 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9772 ; free virtual = 44969 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9764 ; free virtual = 44961 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9748 ; free virtual = 44945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9743 ; free virtual = 44940 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9737 ; free virtual = 44934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9734 ; free virtual = 44931 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9733 ; free virtual = 44930 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9729 ; free virtual = 44926 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9731 ; free virtual = 44928 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:59:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2468.363 ; gain = 341.105 ; free physical = 9709 ; free virtual = 44906 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:59:18 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9718 ; free virtual = 44915 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9718 ; free virtual = 44915 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9718 ; free virtual = 44915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9718 ; free virtual = 44915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9718 ; free virtual = 44915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9720 ; free virtual = 44917 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9726 ; free virtual = 44923 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 9732 ; free virtual = 44929 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 9738 ; free virtual = 44935 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 21873 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2131.426 ; gain = 32.227 ; free physical = 10551 ; free virtual = 45749 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2137.414 ; gain = 38.215 ; free physical = 10481 ; free virtual = 45679 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2137.414 ; gain = 38.215 ; free physical = 10481 ; free virtual = 45678 INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10505 ; free virtual = 45703 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10502 ; free virtual = 45700 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10497 ; free virtual = 45695 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10495 ; free virtual = 45693 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10486 ; free virtual = 45684 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10485 ; free virtual = 45683 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10485 ; free virtual = 45683 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10529 ; free virtual = 45727 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10527 ; free virtual = 45725 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10529 ; free virtual = 45727 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 10558 ; free virtual = 45756 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2194.258 ; gain = 95.059 ; free physical = 10557 ; free virtual = 45755 Writing placer database... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 10529 ; free virtual = 45730 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 10381 ; free virtual = 45592 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string Creating bitstream... INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10369 ; free virtual = 45585 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 10361 ; free virtual = 45577 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10361 ; free virtual = 45577 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.078 ; gain = 51.668 ; free physical = 10352 ; free virtual = 45570 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 10351 ; free virtual = 45569 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.258 ; gain = 0.000 ; free physical = 10335 ; free virtual = 45555 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2.1 Fix Topology Constraints | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 10271 ; free virtual = 45492 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 10267 ; free virtual = 45488 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 10251 ; free virtual = 45472 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 10250 ; free virtual = 45471 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10134 ; free virtual = 45334 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3 Initial Routing | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10240 ; free virtual = 45452 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10237 ; free virtual = 45454 Phase 4 Rip-up And Reroute | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10225 ; free virtual = 45444 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10215 ; free virtual = 45437 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10211 ; free virtual = 45433 Phase 6 Post Hold Fix | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10206 ; free virtual = 45429 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10276 ; free virtual = 45500 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10279 ; free virtual = 45502 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10326 ; free virtual = 45531 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 9 Depositing Routes | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10466 ; free virtual = 45671 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.871 ; gain = 93.461 ; free physical = 10518 ; free virtual = 45723 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:53 . Memory (MB): peak = 2216.660 ; gain = 164.266 ; free physical = 10517 ; free virtual = 45722 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing placer database... INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:13 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 10582 ; free virtual = 45811 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 10556 ; free virtual = 45786 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 10528 ; free virtual = 45741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 10527 ; free virtual = 45740 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 10317 ; free virtual = 45540 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] Command: report_drc (run_mandatory_drcs) for: placer_checks WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 10325 ; free virtual = 45552 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:59:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 2470.145 ; gain = 341.105 ; free physical = 10319 ; free virtual = 45546 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:59:31 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 10325 ; free virtual = 45552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 10335 ; free virtual = 45562 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 10379 ; free virtual = 45607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1543.855 ; gain = 0.000 ; free physical = 11214 ; free virtual = 46443 Writing XDEF routing. Bitstream size: 4243411 bytes Writing XDEF routing logical nets. Writing XDEF routing special nets. Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.58 . Memory (MB): peak = 1543.855 ; gain = 0.000 ; free physical = 11182 ; free virtual = 46416 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2216.660 ; gain = 0.000 ; free physical = 11182 ; free virtual = 46416 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 11165 ; free virtual = 46401 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 11114 ; free virtual = 46351 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 22072 Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2216.660 ; gain = 0.000 ; free physical = 11119 ; free virtual = 46330 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11076 ; free virtual = 46286 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 11057 ; free virtual = 46267 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 11048 ; free virtual = 46258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10986 ; free virtual = 46196 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10985 ; free virtual = 46195 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10980 ; free virtual = 46190 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10979 ; free virtual = 46189 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10975 ; free virtual = 46186 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10972 ; free virtual = 46182 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10969 ; free virtual = 46179 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 10965 ; free virtual = 46175 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 10965 ; free virtual = 46175 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1352.070 ; gain = 256.152 ; free physical = 10806 ; free virtual = 46016 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1360.102 ; gain = 264.184 ; free physical = 10687 ; free virtual = 45897 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1360.102 ; gain = 264.184 ; free physical = 10610 ; free virtual = 45820 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 10546 ; free virtual = 45756 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10533 ; free virtual = 45743 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 10520 ; free virtual = 45730 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 10498 ; free virtual = 45708 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10493 ; free virtual = 45703 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 10450 ; free virtual = 45660 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 10450 ; free virtual = 45660 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10439 ; free virtual = 45649 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10423 ; free virtual = 45633 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10398 ; free virtual = 45608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10395 ; free virtual = 45605 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10392 ; free virtual = 45603 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10392 ; free virtual = 45602 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10391 ; free virtual = 45601 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10390 ; free virtual = 45600 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10390 ; free virtual = 45600 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10389 ; free virtual = 45599 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10389 ; free virtual = 45599 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10385 ; free virtual = 45595 Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10385 ; free virtual = 45595 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10381 ; free virtual = 45591 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 10376 ; free virtual = 45587 Synthesis Optimization Runtime : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.078 ; gain = 272.160 ; free physical = 10371 ; free virtual = 45581 Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1368.086 ; gain = 272.160 ; free physical = 10370 ; free virtual = 45580 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 10366 ; free virtual = 45576 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 10179 ; free virtual = 45389 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... Loading route data... Processing options... Creating bitmap... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 22197 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 9866 ; free virtual = 45076 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9739 ; free virtual = 44949 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9733 ; free virtual = 44944 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9733 ; free virtual = 44943 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9732 ; free virtual = 44943 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9729 ; free virtual = 44939 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.254 ; gain = 468.531 ; free physical = 9728 ; free virtual = 44938 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 9727 ; free virtual = 44938 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 9426 ; free virtual = 44637 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:16] INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9356 ; free virtual = 44567 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.953 ; gain = 0.000 ; free physical = 9360 ; free virtual = 44571 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1470.953 ; gain = 0.000 ; free physical = 9367 ; free virtual = 44577 Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 9305 ; free virtual = 44520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 9303 ; free virtual = 44518 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 8980 ; free virtual = 44195 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 8802 ; free virtual = 44017 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 8814 ; free virtual = 44029 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 07:59:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2533.363 ; gain = 339.105 ; free physical = 8793 ; free virtual = 44008 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 07:59:53 2019... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 8881 ; free virtual = 44095 Phase 1.3 Build Placer Netlist Model Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 9270 ; free virtual = 44485 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 Phase 1 Build RT Design | Checksum: 1b23f6d9e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2134.082 ; gain = 49.668 ; free physical = 9644 ; free virtual = 44858 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:330] Phase 2.1 Fix Topology Constraints WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2.1 Fix Topology Constraints | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2143.070 ; gain = 58.656 ; free physical = 9499 ; free virtual = 44714 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2143.070 ; gain = 58.656 ; free physical = 9545 ; free virtual = 44760 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:919] Loading site data... WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.387 ; gain = 508.531 ; free physical = 9516 ; free virtual = 44740 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9497 ; free virtual = 44712 --------------------------------------------------------------------------------- Loading route data... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1cdf75140 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9506 ; free virtual = 44723 Phase 3 Initial Routing Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 9484 ; free virtual = 44699 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9483 ; free virtual = 44699 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 9465 ; free virtual = 44680 Phase 1.4 Constrain Clocks/Macros INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9454 ; free virtual = 44670 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 9446 ; free virtual = 44661 Phase 4.1 Global Iteration 0 | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9445 ; free virtual = 44660 Phase 4 Rip-up And Reroute | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9443 ; free virtual = 44658 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9440 ; free virtual = 44656 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9437 ; free virtual = 44653 Phase 6 Post Hold Fix | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9433 ; free virtual = 44649 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 9389 ; free virtual = 44604 Phase 2 Global Placement Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9411 ; free virtual = 44626 Phase 8 Verifying routed nets Verification completed successfully --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 9408 ; free virtual = 44623 --------------------------------------------------------------------------------- Phase 8 Verifying routed nets | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9407 ; free virtual = 44623 Phase 9 Depositing Routes Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 22473 Phase 9 Depositing Routes | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9369 ; free virtual = 44589 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 9411 ; free virtual = 44632 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:51 . Memory (MB): peak = 2217.789 ; gain = 165.391 ; free physical = 9410 ; free virtual = 44631 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9344 ; free virtual = 44565 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 9327 ; free virtual = 44551 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9248 ; free virtual = 44477 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9195 ; free virtual = 44427 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9152 ; free virtual = 44385 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9138 ; free virtual = 44373 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 508.531 ; free physical = 9134 ; free virtual = 44369 Phase 1.4 Constrain Clocks/Macros Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9136 ; free virtual = 44371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 508.531 ; free physical = 9128 ; free virtual = 44363 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9126 ; free virtual = 44361 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9122 ; free virtual = 44357 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9105 ; free virtual = 44341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9088 ; free virtual = 44324 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 508.531 ; free physical = 9088 ; free virtual = 44324 |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9079 ; free virtual = 44314 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 9056 ; free virtual = 44292 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 9052 ; free virtual = 44288 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 508.531 ; free physical = 9015 ; free virtual = 44251 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9014 ; free virtual = 44250 Phase 3.3 Area Swap Optimization Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 508.531 ; free physical = 8922 ; free virtual = 44160 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 8918 ; free virtual = 44156 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8911 ; free virtual = 44150 Phase 3.4 Pipeline Register Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 8907 ; free virtual = 44146 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8883 ; free virtual = 44125 Phase 3.5 Small Shape Detail Placement Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2217.789 ; gain = 0.000 ; free physical = 8873 ; free virtual = 44117 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.789 ; gain = 0.000 ; free physical = 8833 ; free virtual = 44051 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 8807 ; free virtual = 44025 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 8800 ; free virtual = 44019 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 8800 ; free virtual = 44018 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 8799 ; free virtual = 44017 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 8796 ; free virtual = 44014 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 8796 ; free virtual = 44015 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 8796 ; free virtual = 44014 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-570] Preparing netlist for logic optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8804 ; free virtual = 44023 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8804 ; free virtual = 44023 Phase 3.7 Pipeline Register Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8751 ; free virtual = 43969 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.684 ; gain = 215.238 ; free physical = 8704 ; free virtual = 43923 --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8703 ; free virtual = 43922 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8690 ; free virtual = 43908 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8667 ; free virtual = 43886 Phase 4.3 Placer Reporting Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1310.684 ; gain = 215.238 ; free physical = 8706 ; free virtual = 43924 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8696 ; free virtual = 43915 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8695 ; free virtual = 43913 Phase 4.4 Final Placement Cleanup INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8677 ; free virtual = 43896 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:14 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 8699 ; free virtual = 43917 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8669 ; free virtual = 43888 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 8659 ; free virtual = 43877 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 8664 ; free virtual = 43882 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.199 ; gain = 623.949 ; free physical = 8664 ; free virtual = 43882 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8607 ; free virtual = 43825 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8600 ; free virtual = 43819 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8597 ; free virtual = 43816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8594 ; free virtual = 43812 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8585 ; free virtual = 43804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8583 ; free virtual = 43802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8582 ; free virtual = 43801 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 8574 ; free virtual = 43793 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 8573 ; free virtual = 43791 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1902.441 ; gain = 0.000 ; free physical = 8328 ; free virtual = 43547 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 8358 ; free virtual = 43577 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 8372 ; free virtual = 43592 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 8371 ; free virtual = 43592 --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 8365 ; free virtual = 43588 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Starting Routing Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 519.531 ; free physical = 8397 ; free virtual = 43620 Phase 1.3 Build Placer Netlist Model Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 519.531 ; free physical = 8421 ; free virtual = 43644 Phase 1.4 Constrain Clocks/Macros Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 519.531 ; free physical = 8500 ; free virtual = 43723 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 519.531 ; free physical = 8601 ; free virtual = 43824 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 519.531 ; free physical = 8599 ; free virtual = 43822 Phase 1 Placer Initialization INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 519.531 ; free physical = 8578 ; free virtual = 43801 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1990.484 ; gain = 583.562 ; free physical = 8572 ; free virtual = 43795 Phase 1.1 Placer Initialization Netlist Sorting Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1557.859 ; gain = 0.000 ; free physical = 8567 ; free virtual = 43790 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.60 . Memory (MB): peak = 1557.859 ; gain = 0.000 ; free physical = 8602 ; free virtual = 43825 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:45 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 8204 ; free virtual = 43427 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:00:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:44 . Memory (MB): peak = 2606.820 ; gain = 390.160 ; free physical = 8254 ; free virtual = 43477 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:00:17 2019... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Placer Task INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 9048 ; free virtual = 44271 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 9047 ; free virtual = 44270 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1550.953 ; gain = 0.000 ; free physical = 9016 ; free virtual = 44239 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 9002 ; free virtual = 44225 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 8990 ; free virtual = 44213 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 8831 ; free virtual = 44054 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1303.680 ; gain = 208.242 ; free physical = 8841 ; free virtual = 44064 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8833 ; free virtual = 44056 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8724 ; free virtual = 43947 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8723 ; free virtual = 43946 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8722 ; free virtual = 43945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8722 ; free virtual = 43945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8722 ; free virtual = 43945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8722 ; free virtual = 43945 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8710 ; free virtual = 43933 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.656 ; gain = 216.219 ; free physical = 8703 ; free virtual = 43926 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 8704 ; free virtual = 43927 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23426 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 8384 ; free virtual = 43607 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.711 ; gain = 0.000 ; free physical = 8296 ; free virtual = 43519 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1461.711 ; gain = 0.000 ; free physical = 8296 ; free virtual = 43519 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 7767 ; free virtual = 42990 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: eb6f845d Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2057.938 ; gain = 93.668 ; free physical = 7739 ; free virtual = 42962 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: eb6f845d Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2062.926 ; gain = 98.656 ; free physical = 7779 ; free virtual = 43002 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: eb6f845d Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 2062.926 ; gain = 98.656 ; free physical = 7779 ; free virtual = 43002 INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7738 ; free virtual = 42961 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7722 ; free virtual = 42945 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7722 ; free virtual = 42945 Phase 4 Rip-up And Reroute | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7722 ; free virtual = 42945 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7722 ; free virtual = 42945 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7722 ; free virtual = 42945 Phase 6 Post Hold Fix | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:50 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7722 ; free virtual = 42945 Phase 7 Route finalize INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6c93b630 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 7750 ; free virtual = 42973 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6c93b630 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 7748 ; free virtual = 42971 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6c93b630 Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 7748 ; free virtual = 42971 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:51 . Memory (MB): peak = 2072.980 ; gain = 108.711 ; free physical = 7781 ; free virtual = 43004 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2111.770 ; gain = 179.516 ; free physical = 7781 ; free virtual = 43004 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 7777 ; free virtual = 43000 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2111.770 ; gain = 0.000 ; free physical = 7759 ; free virtual = 42984 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7730 ; free virtual = 42953 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7753 ; free virtual = 42976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7754 ; free virtual = 42978 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7775 ; free virtual = 42999 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 7520 ; free virtual = 42743 Phase 1.3 Build Placer Netlist Model WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 7100 ; free virtual = 42323 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 6974 ; free virtual = 42198 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 6975 ; free virtual = 42198 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 6965 ; free virtual = 42188 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 6955 ; free virtual = 42178 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 6948 ; free virtual = 42172 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 6948 ; free virtual = 42172 INFO: [Timing 38-35] Done setting XDC timing constraints. 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 6950 ; free virtual = 42173 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 6930 ; free virtual = 42154 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading data files... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 6768 ; free virtual = 41991 Phase 1.4 Constrain Clocks/Macros Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 6761 ; free virtual = 41985 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 6754 ; free virtual = 41977 Writing bitstream ./design.bit... Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 6720 ; free virtual = 41944 Phase 2 Final Placement Cleanup INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 23601 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 6743 ; free virtual = 41971 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.391 ; gain = 494.531 ; free physical = 6974 ; free virtual = 42202 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 6997 ; free virtual = 42225 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 6907 ; free virtual = 42135 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 6895 ; free virtual = 42123 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6894 ; free virtual = 42122 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6912 ; free virtual = 42139 --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6912 ; free virtual = 42139 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6901 ; free virtual = 42129 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6901 ; free virtual = 42129 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6901 ; free virtual = 42129 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6901 ; free virtual = 42129 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6901 ; free virtual = 42129 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6901 ; free virtual = 42128 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 6902 ; free virtual = 42130 INFO: [Project 1-571] Translating synthesized netlist Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 6866 ; free virtual = 42094 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 6863 ; free virtual = 42091 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 2003.156 ; gain = 452.203 ; free physical = 6848 ; free virtual = 42075 Phase 2 Global Placement INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.070 ; gain = 51.668 ; free physical = 6784 ; free virtual = 42012 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:00:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2606.949 ; gain = 389.160 ; free physical = 6781 ; free virtual = 42008 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:00:50 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e9c56990 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2146.059 ; gain = 61.656 ; free physical = 6797 ; free virtual = 42023 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e9c56990 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2146.059 ; gain = 61.656 ; free physical = 6803 ; free virtual = 42029 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_014 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7694 ; free virtual = 42922 Phase 3 Initial Routing WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7434 ; free virtual = 42662 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7431 ; free virtual = 42659 Phase 4 Rip-up And Reroute | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7449 ; free virtual = 42677 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7443 ; free virtual = 42670 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7435 ; free virtual = 42663 Phase 6 Post Hold Fix | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7430 ; free virtual = 42657 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 7 Route finalize INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 7416 ; free virtual = 42644 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7411 ; free virtual = 42638 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7415 ; free virtual = 42643 Phase 9 Depositing Routes Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7421 ; free virtual = 42649 Phase 9 Depositing Routes | Checksum: 16f7d8d1d Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7420 ; free virtual = 42649 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.988 ; gain = 95.586 ; free physical = 7463 ; free virtual = 42692 Routing Is Done. Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2218.777 ; gain = 166.391 ; free physical = 7463 ; free virtual = 42691 Writing placer database... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7400 ; free virtual = 42630 Phase 3.2 Commit Most Macros & LUTRAMs Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 7394 ; free virtual = 42627 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 7390 ; free virtual = 42623 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 7390 ; free virtual = 42622 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 7389 ; free virtual = 42621 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 7388 ; free virtual = 42621 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 7387 ; free virtual = 42619 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 7387 ; free virtual = 42619 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7349 ; free virtual = 42583 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3.3 Area Swap Optimization 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 7351 ; free virtual = 42586 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7332 ; free virtual = 42569 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7317 ; free virtual = 42556 Phase 3.5 Small Shape Detail Placement Loading site data... Phase 1 Build RT Design | Checksum: 1307d6b8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 7315 ; free virtual = 42555 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1307d6b8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 7278 ; free virtual = 42518 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1307d6b8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.918 ; gain = 98.656 ; free physical = 7276 ; free virtual = 42516 Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7202 ; free virtual = 42445 Phase 3 Initial Routing Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 7202 ; free virtual = 42445 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 7199 ; free virtual = 42443 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 7188 ; free virtual = 42433 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7184 ; free virtual = 42431 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7178 ; free virtual = 42424 Phase 4 Rip-up And Reroute | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7178 ; free virtual = 42424 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7178 ; free virtual = 42424 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7178 ; free virtual = 42424 Phase 6 Post Hold Fix | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7178 ; free virtual = 42424 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 7163 ; free virtual = 42411 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 7161 ; free virtual = 42410 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d37d05e Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 7160 ; free virtual = 42408 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 7192 ; free virtual = 42440 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:52 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 7190 ; free virtual = 42439 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2128.961 ; gain = 37.762 ; free physical = 7182 ; free virtual = 42430 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Writing placer database... Phase 2.1 Fix Topology Constraints Writing XDEF routing. Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.949 ; gain = 43.750 ; free physical = 7139 ; free virtual = 42389 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.949 ; gain = 43.750 ; free physical = 7139 ; free virtual = 42389 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 7128 ; free virtual = 42379 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7098 ; free virtual = 42348 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7055 ; free virtual = 42307 Phase 3.7 Pipeline Register Optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.777 ; gain = 0.000 ; free physical = 6998 ; free virtual = 42255 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 6994 ; free virtual = 42251 Phase 3 Initial Routing Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 6982 ; free virtual = 42239 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7040 ; free virtual = 42298 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7036 ; free virtual = 42294 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7033 ; free virtual = 42291 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7033 ; free virtual = 42291 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7033 ; free virtual = 42292 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7033 ; free virtual = 42291 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7033 ; free virtual = 42291 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7023 ; free virtual = 42281 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7023 ; free virtual = 42281 Phase 9 Depositing Routes Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7023 ; free virtual = 42281 Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7020 ; free virtual = 42278 WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 7055 ; free virtual = 42314 Routing Is Done. WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:49 . Memory (MB): peak = 2191.793 ; gain = 100.594 ; free physical = 7055 ; free virtual = 42314 WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] Phase 4.2 Post Placement Cleanup WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing placer database... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2218.777 ; gain = 0.000 ; free physical = 7060 ; free virtual = 42293 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7059 ; free virtual = 42292 Phase 4.3 Placer Reporting INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7078 ; free virtual = 42312 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 7063 ; free virtual = 42298 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 7033 ; free virtual = 42269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 7032 ; free virtual = 42268 --------------------------------------------------------------------------------- Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7029 ; free virtual = 42265 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 7037 ; free virtual = 42274 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7051 ; free virtual = 42288 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.203 ; gain = 548.250 ; free physical = 7087 ; free virtual = 42326 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.203 ; gain = 630.953 ; free physical = 7086 ; free virtual = 42324 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2066.168 ; gain = 43.668 ; free physical = 7263 ; free virtual = 42510 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2072.156 ; gain = 49.656 ; free physical = 7212 ; free virtual = 42459 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2072.156 ; gain = 49.656 ; free physical = 7209 ; free virtual = 42456 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2083.461 ; gain = 60.961 ; free physical = 7215 ; free virtual = 42466 Phase 3 Initial Routing WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7226 ; free virtual = 42480 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7232 ; free virtual = 42486 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7233 ; free virtual = 42487 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7233 ; free virtual = 42487 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7232 ; free virtual = 42486 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7232 ; free virtual = 42486 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2084.461 ; gain = 61.961 ; free physical = 7202 ; free virtual = 42457 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2087.461 ; gain = 64.961 ; free physical = 7199 ; free virtual = 42454 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 7187 ; free virtual = 42443 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:50 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 7222 ; free virtual = 42478 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:51 . Memory (MB): peak = 2127.250 ; gain = 136.766 ; free physical = 7221 ; free virtual = 42477 Writing placer database... Writing XDEF routing. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing logical nets. Writing XDEF routing special nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2191.793 ; gain = 0.000 ; free physical = 7203 ; free virtual = 42465 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Write XDEF Complete: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2127.250 ; gain = 0.000 ; free physical = 7211 ; free virtual = 42474 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2191.793 ; gain = 0.000 ; free physical = 7148 ; free virtual = 42386 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:01:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2456.875 ; gain = 345.105 ; free physical = 7053 ; free virtual = 42291 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:01:06 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_015 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 7681 ; free virtual = 42921 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 7625 ; free virtual = 42864 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7633 ; free virtual = 42872 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7481 ; free virtual = 42721 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7477 ; free virtual = 42717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7475 ; free virtual = 42714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7475 ; free virtual = 42714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7475 ; free virtual = 42714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7474 ; free virtual = 42714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7474 ; free virtual = 42714 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 7473 ; free virtual = 42712 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 7473 ; free virtual = 42713 INFO: [Project 1-571] Translating synthesized netlist Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading data files... INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24692 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 6354 ; free virtual = 41593 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 6356 ; free virtual = 41596 INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 6264 ; free virtual = 41504 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 6262 ; free virtual = 41501 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 6288 ; free virtual = 41527 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 6286 ; free virtual = 41525 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 6285 ; free virtual = 41525 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 6287 ; free virtual = 41526 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 6287 ; free virtual = 41526 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1470.965 ; gain = 0.000 ; free physical = 6245 ; free virtual = 41485 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1470.965 ; gain = 0.000 ; free physical = 6242 ; free virtual = 41482 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... Loading site data... Loading site data... Loading route data... Loading route data... Processing options... Creating bitmap... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:01:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2453.867 ; gain = 343.105 ; free physical = 6087 ; free virtual = 41331 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:01:26 2019... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 Creating bitstream... Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 7042 ; free virtual = 42289 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1 Build RT Design | Checksum: 15af38611 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.953 ; gain = 42.668 ; free physical = 7176 ; free virtual = 42423 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15af38611 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 7141 ; free virtual = 42388 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15af38611 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 7141 ; free virtual = 42388 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10d853c8e Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2087.246 ; gain = 60.961 ; free physical = 7117 ; free virtual = 42369 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7266 ; free virtual = 42517 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7355 ; free virtual = 42607 Phase 4 Rip-up And Reroute | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7356 ; free virtual = 42608 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7355 ; free virtual = 42607 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7361 ; free virtual = 42612 Phase 6 Post Hold Fix | Checksum: 10d853c8e Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7367 ; free virtual = 42619 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: Launching helper process for spawning children vivado processes INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: Helper process launched with PID 24881 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2088.246 ; gain = 61.961 ; free physical = 7396 ; free virtual = 42648 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 7403 ; free virtual = 42654 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10d853c8e Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 7370 ; free virtual = 42622 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 7407 ; free virtual = 42659 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2130.035 ; gain = 135.766 ; free physical = 7408 ; free virtual = 42660 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:01:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2469.355 ; gain = 342.105 ; free physical = 7408 ; free virtual = 42661 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:01:34 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2130.035 ; gain = 0.000 ; free physical = 7377 ; free virtual = 42633 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:16] Phase 1 Build RT Design | Checksum: 118b3be9c Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2137.074 ; gain = 52.668 ; free physical = 8316 ; free virtual = 43569 Creating bitstream... WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 118b3be9c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2147.062 ; gain = 62.656 ; free physical = 8309 ; free virtual = 43563 Phase 2.2 Pre Route Cleanup INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:01:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 2.2 Pre Route Cleanup | Checksum: 118b3be9c Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2147.062 ; gain = 62.656 ; free physical = 8308 ; free virtual = 43564 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2531.398 ; gain = 339.605 ; free physical = 8306 ; free virtual = 43564 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:01:37 2019... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8360 ; free virtual = 43612 --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9297 ; free virtual = 44551 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9296 ; free virtual = 44549 --------------------------------------------------------------------------------- touch build/specimen_012/OK Phase 2 Router Initialization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9301 ; free virtual = 44555 Phase 3 Initial Routing GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9279 ; free virtual = 44533 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9257 ; free virtual = 44511 Phase 4 Rip-up And Reroute | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9248 ; free virtual = 44501 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9236 ; free virtual = 44490 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9232 ; free virtual = 44485 Phase 6 Post Hold Fix | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9229 ; free virtual = 44483 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9241 ; free virtual = 44495 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 145a2d7e1 Time (s): cpu = 00:00:44 ; elapsed = 00:00:50 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9221 ; free virtual = 44475 Phase 9 Depositing Routes INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 9 Depositing Routes | Checksum: 145a2d7e1 Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9216 ; free virtual = 44470 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2181.992 ; gain = 97.586 ; free physical = 9254 ; free virtual = 44508 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:53 . Memory (MB): peak = 2220.781 ; gain = 168.391 ; free physical = 9253 ; free virtual = 44507 Writing bitstream ./design.bit... Writing placer database... Loading data files... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 9478 ; free virtual = 44746 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2220.781 ; gain = 0.000 ; free physical = 8953 ; free virtual = 44239 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.453 ; gain = 0.000 ; free physical = 8951 ; free virtual = 44238 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 8948 ; free virtual = 44235 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 520.531 ; free physical = 8994 ; free virtual = 44282 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 520.531 ; free physical = 8988 ; free virtual = 44276 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 520.531 ; free physical = 8988 ; free virtual = 44276 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 520.531 ; free physical = 8984 ; free virtual = 44272 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 520.531 ; free physical = 8978 ; free virtual = 44267 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.496 ; gain = 520.531 ; free physical = 8976 ; free virtual = 44265 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.496 ; gain = 584.562 ; free physical = 8975 ; free virtual = 44264 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:01:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1 Build RT Design | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2057.926 ; gain = 93.668 ; free physical = 8917 ; free virtual = 44178 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:45 . Memory (MB): peak = 2607.938 ; gain = 389.160 ; free physical = 8916 ; free virtual = 44177 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:01:44 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 8882 ; free virtual = 44141 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 133887d51 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 8882 ; free virtual = 44141 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10025 ; free virtual = 45284 Phase 3 Initial Routing Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10011 ; free virtual = 45271 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f6c26eb9 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10010 ; free virtual = 45270 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] Phase 4 Rip-up And Reroute | Checksum: f6c26eb9 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10010 ; free virtual = 45270 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] Phase 5 Delay and Skew Optimization WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 5 Delay and Skew Optimization | Checksum: f6c26eb9 WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10010 ; free virtual = 45270 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10010 ; free virtual = 45270 Phase 6 Post Hold Fix | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 10010 ; free virtual = 45270 Running DRC as a precondition to command write_bitstream Phase 7 Route finalize Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 9984 ; free virtual = 45245 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 9983 ; free virtual = 45243 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 9982 ; free virtual = 45242 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2071.969 ; gain = 107.711 ; free physical = 10014 ; free virtual = 45274 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:51 . Memory (MB): peak = 2110.758 ; gain = 178.516 ; free physical = 10012 ; free virtual = 45272 Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 Writing placer database... Writing XDEF routing. Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2110.758 ; gain = 0.000 ; free physical = 10015 ; free virtual = 45277 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9887 ; free virtual = 45148 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 9879 ; free virtual = 45140 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9860 ; free virtual = 45121 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9731 ; free virtual = 44992 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9723 ; free virtual = 44985 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:16] --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9706 ; free virtual = 44968 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9702 ; free virtual = 44963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9696 ; free virtual = 44958 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9693 ; free virtual = 44955 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9691 ; free virtual = 44952 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 9684 ; free virtual = 44945 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 9683 ; free virtual = 44944 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading site data... --------------------------------------------------------------------------------- Loading route data... Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 9588 ; free virtual = 44850 --------------------------------------------------------------------------------- Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 9593 ; free virtual = 44855 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 9545 ; free virtual = 44812 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 9544 ; free virtual = 44812 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 9503 ; free virtual = 44765 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 9502 ; free virtual = 44764 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9409 ; free virtual = 44671 Phase 3 Initial Routing WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25216 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9375 ; free virtual = 44637 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9362 ; free virtual = 44623 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9362 ; free virtual = 44623 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9362 ; free virtual = 44623 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9362 ; free virtual = 44623 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9362 ; free virtual = 44623 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9272 ; free virtual = 44533 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9269 ; free virtual = 44531 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9264 ; free virtual = 44526 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:49 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 9300 ; free virtual = 44561 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:52 . Memory (MB): peak = 2195.262 ; gain = 96.059 ; free physical = 9298 ; free virtual = 44560 Writing placer database... Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1268.090 ; gain = 172.469 ; free physical = 9090 ; free virtual = 44365 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2195.262 ; gain = 0.000 ; free physical = 8865 ; free virtual = 44150 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2195.262 ; gain = 0.000 ; free physical = 8797 ; free virtual = 44060 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25280 Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.684 ; gain = 249.062 ; free physical = 8543 ; free virtual = 43806 --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 8543 ; free virtual = 43806 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.684 ; gain = 249.062 ; free physical = 8548 ; free virtual = 43812 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8457 ; free virtual = 43721 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 8456 ; free virtual = 43720 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: Launching helper process for spawning children vivado processes Starting Placer Task INFO: Helper process launched with PID 25356 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1545.949 ; gain = 0.000 ; free physical = 8685 ; free virtual = 43953 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8699 ; free virtual = 43966 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8689 ; free virtual = 43957 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1545.949 ; gain = 0.000 ; free physical = 8691 ; free virtual = 43958 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8698 ; free virtual = 43966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8689 ; free virtual = 43957 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8684 ; free virtual = 43952 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8672 ; free virtual = 43940 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8677 ; free virtual = 43945 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.707 ; gain = 270.086 ; free physical = 8641 ; free virtual = 43909 Synthesis Optimization Complete : Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.715 ; gain = 270.086 ; free physical = 8659 ; free virtual = 43927 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 8542 ; free virtual = 43810 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 8521 ; free virtual = 43789 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 8519 ; free virtual = 43787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 8481 ; free virtual = 43749 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 8476 ; free virtual = 43744 Loading route data... Processing options... Creating bitmap... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 8438 ; free virtual = 43706 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 8441 ; free virtual = 43709 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 8358 ; free virtual = 43626 Phase 3 Initial Routing WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8318 ; free virtual = 43586 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8316 ; free virtual = 43583 Loading data files... Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8315 ; free virtual = 43582 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8313 ; free virtual = 43581 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8312 ; free virtual = 43580 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8312 ; free virtual = 43580 Phase 7 Route finalize INFO: [Project 1-570] Preparing netlist for logic optimization Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8308 ; free virtual = 43575 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 8305 ; free virtual = 43573 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 8295 ; free virtual = 43563 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 8332 ; free virtual = 43600 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 8330 ; free virtual = 43598 Writing placer database... Creating bitstream... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 8269 ; free virtual = 43540 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:02:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2470.141 ; gain = 340.105 ; free physical = 8148 ; free virtual = 43416 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:02:07 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 9089 ; free virtual = 44358 --------------------------------------------------------------------------------- Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top touch build/specimen_013/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_016 Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Command: synth_design -top top Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Starting synth_design Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Using part: xc7z020clg400-1 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4047] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1002] INFO: [Vivado 12-1842] Bitgen Completed Successfully. WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Helper process launched with PID 25489 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9144 ; free virtual = 44419 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 9100 ; free virtual = 44376 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 9100 ; free virtual = 44375 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 8978 ; free virtual = 44253 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.445 ; gain = 55.992 ; free physical = 8897 ; free virtual = 44172 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 8884 ; free virtual = 44159 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 8864 ; free virtual = 44140 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 8858 ; free virtual = 44133 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:02:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2453.863 ; gain = 343.105 ; free physical = 8859 ; free virtual = 44135 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:02:15 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9748 ; free virtual = 45024 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9748 ; free virtual = 45023 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9746 ; free virtual = 45021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9746 ; free virtual = 45021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9746 ; free virtual = 45021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9743 ; free virtual = 45018 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9742 ; free virtual = 45018 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 9740 ; free virtual = 45016 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9732 ; free virtual = 45008 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.379 ; gain = 384.484 ; free physical = 9629 ; free virtual = 44904 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9634 ; free virtual = 44910 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1211.953 ; gain = 116.500 ; free physical = 9538 ; free virtual = 44814 Loading route data... --------------------------------------------------------------------------------- Processing options... --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Creating bitmap... --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9535 ; free virtual = 44811 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 1219.980 ; gain = 124.527 ; free physical = 9477 ; free virtual = 44754 --------------------------------------------------------------------------------- Starting Placer Task Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1547.082 ; gain = 0.000 ; free physical = 9458 ; free virtual = 44734 Creating bitstream... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.66 . Memory (MB): peak = 1547.082 ; gain = 0.000 ; free physical = 9416 ; free virtual = 44692 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9405 ; free virtual = 44681 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 9402 ; free virtual = 44678 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 9362 ; free virtual = 44638 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9375 ; free virtual = 44651 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 1397.680 ; gain = 314.797 ; free physical = 9384 ; free virtual = 44660 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Writing bitstream ./design.bit... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9642 ; free virtual = 44922 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9641 ; free virtual = 44921 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9637 ; free virtual = 44917 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9636 ; free virtual = 44916 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9635 ; free virtual = 44915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9635 ; free virtual = 44915 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9634 ; free virtual = 44914 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 9628 ; free virtual = 44908 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 9634 ; free virtual = 44914 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.711 ; gain = 0.000 ; free physical = 9633 ; free virtual = 44913 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1461.711 ; gain = 0.000 ; free physical = 9634 ; free virtual = 44914 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9638 ; free virtual = 44918 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9658 ; free virtual = 44939 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9658 ; free virtual = 44939 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9659 ; free virtual = 44940 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading route data... Processing options... Creating bitmap... INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.691 ; gain = 215.238 ; free physical = 9384 ; free virtual = 44669 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:02:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:43 . Memory (MB): peak = 2608.941 ; gain = 388.160 ; free physical = 9394 ; free virtual = 44679 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:02:27 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.691 ; gain = 215.238 ; free physical = 9457 ; free virtual = 44740 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 9506 ; free virtual = 44789 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 10472 ; free virtual = 45756 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:02:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2533.367 ; gain = 338.105 ; free physical = 10419 ; free virtual = 45704 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:02:28 2019... Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10465 ; free virtual = 45749 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10486 ; free virtual = 45770 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10491 ; free virtual = 45774 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10495 ; free virtual = 45778 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10494 ; free virtual = 45777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10494 ; free virtual = 45777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10556 ; free virtual = 45840 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 10680 ; free virtual = 45963 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.691 ; gain = 225.230 ; free physical = 10767 ; free virtual = 46051 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.180 ; gain = 43.668 ; free physical = 11357 ; free virtual = 46646 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 11309 ; free virtual = 46599 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 11308 ; free virtual = 46597 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.152 ; gain = 457.203 ; free physical = 11278 ; free virtual = 46567 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.473 ; gain = 60.961 ; free physical = 11184 ; free virtual = 46473 Phase 3 Initial Routing INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 11274 ; free virtual = 46565 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11286 ; free virtual = 46581 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11289 ; free virtual = 46584 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11288 ; free virtual = 46582 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11287 ; free virtual = 46581 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11287 ; free virtual = 46581 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11286 ; free virtual = 46580 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2085.473 ; gain = 61.961 ; free physical = 11262 ; free virtual = 46556 Phase 8 Verifying routed nets Verification completed successfully INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.473 ; gain = 64.961 ; free physical = 11237 ; free virtual = 46532 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.473 ; gain = 65.961 ; free physical = 11206 ; free virtual = 46500 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.473 ; gain = 65.961 ; free physical = 11240 ; free virtual = 46534 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2128.262 ; gain = 136.766 ; free physical = 11237 ; free virtual = 46531 Writing placer database... Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2128.262 ; gain = 0.000 ; free physical = 11274 ; free virtual = 46579 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11550 ; free virtual = 46849 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 11550 ; free virtual = 46849 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 11541 ; free virtual = 46840 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 11537 ; free virtual = 46836 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11517 ; free virtual = 46816 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11513 ; free virtual = 46812 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11513 ; free virtual = 46812 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11513 ; free virtual = 46812 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11511 ; free virtual = 46811 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11511 ; free virtual = 46810 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11511 ; free virtual = 46810 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11512 ; free virtual = 46811 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 11511 ; free virtual = 46810 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 11513 ; free virtual = 46812 INFO: [Project 1-571] Translating synthesized netlist Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 457.203 ; free physical = 11479 ; free virtual = 46779 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 457.203 ; free physical = 11442 ; free virtual = 46741 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 2003.152 ; gain = 457.203 ; free physical = 11416 ; free virtual = 46715 Phase 2 Global Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Command: synth_design -top top INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Starting synth_design Using part: xc7z020clg400-1 INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:02:34 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2472.359 ; gain = 344.105 ; free physical = 11313 ; free virtual = 46612 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:02:34 2019... INFO: Launching helper process for spawning children vivado processes Bitstream size: 4243411 bytes INFO: Helper process launched with PID 26199 Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.715 ; gain = 333.820 ; free physical = 12172 ; free virtual = 47471 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading data files... Starting Placer Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 12033 ; free virtual = 47338 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1482.746 ; gain = 0.000 ; free physical = 12070 ; free virtual = 47375 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 12081 ; free virtual = 47386 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 12060 ; free virtual = 47365 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 12018 ; free virtual = 47322 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11947 ; free virtual = 47252 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11905 ; free virtual = 47210 Phase 3.4 Pipeline Register Optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Placer Task Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11865 ; free virtual = 47170 Phase 3.5 Small Shape Detail Placement INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 11859 ; free virtual = 47164 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 11858 ; free virtual = 47163 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26609 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.570 ; gain = 0.000 ; free physical = 11500 ; free virtual = 46805 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11495 ; free virtual = 46800 Phase 3.6 Re-assign LUT pins Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11454 ; free virtual = 46759 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11364 ; free virtual = 46669 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11266 ; free virtual = 46571 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11137 ; free virtual = 46442 Phase 4.2 Post Placement Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 11193 ; free virtual = 46498 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11180 ; free virtual = 46485 Phase 4.3 Placer Reporting WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11045 ; free virtual = 46350 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11018 ; free virtual = 46323 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.285 ; gain = 456.203 ; free physical = 11008 ; free virtual = 46312 Phase 1.3 Build Placer Netlist Model Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11120 ; free virtual = 46424 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 553.250 ; free physical = 11068 ; free virtual = 46373 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 11067 ; free virtual = 46372 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 11023 ; free virtual = 46328 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 11021 ; free virtual = 46326 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 11021 ; free virtual = 46326 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 11022 ; free virtual = 46327 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 11023 ; free virtual = 46328 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 11023 ; free virtual = 46328 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 11023 ; free virtual = 46328 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 11011 ; free virtual = 46316 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.285 ; gain = 456.203 ; free physical = 10835 ; free virtual = 46141 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.285 ; gain = 456.203 ; free physical = 10792 ; free virtual = 46097 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.285 ; gain = 456.203 ; free physical = 10758 ; free virtual = 46063 Phase 2 Global Placement Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:16] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10209 ; free virtual = 45514 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 10166 ; free virtual = 45472 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 10167 ; free virtual = 45472 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 10183 ; free virtual = 45489 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 10179 ; free virtual = 45487 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 10177 ; free virtual = 45486 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 10174 ; free virtual = 45485 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 10176 ; free virtual = 45488 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 10175 ; free virtual = 45487 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10164 ; free virtual = 45470 --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10156 ; free virtual = 45463 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10122 ; free virtual = 45433 Phase 3.2 Commit Most Macros & LUTRAMs Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 10130 ; free virtual = 45436 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 10130 ; free virtual = 45436 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10156 ; free virtual = 45462 --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10148 ; free virtual = 45454 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10131 ; free virtual = 45437 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10127 ; free virtual = 45433 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10107 ; free virtual = 45413 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10097 ; free virtual = 45403 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10007 ; free virtual = 45313 Phase 3.5 Small Shape Detail Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27453 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27564 Writing bitstream ./design.bit... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9762 ; free virtual = 45072 Phase 3.6 Re-assign LUT pins INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10061 ; free virtual = 45371 Phase 3.7 Pipeline Register Optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1269.285 ; gain = 173.672 ; free physical = 10037 ; free virtual = 45347 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 10029 ; free virtual = 45339 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9980 ; free virtual = 45290 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9952 ; free virtual = 45262 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9901 ; free virtual = 45211 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9886 ; free virtual = 45196 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9851 ; free virtual = 45161 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9821 ; free virtual = 45131 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.328 ; gain = 544.246 ; free physical = 9799 ; free virtual = 45109 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2091.328 ; gain = 623.949 ; free physical = 9790 ; free virtual = 45100 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:02:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2462.438 ; gain = 334.176 ; free physical = 9317 ; free virtual = 44627 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:02:58 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.234 ; gain = 0.000 ; free physical = 9374 ; free virtual = 44685 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 9941 ; free virtual = 45251 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 10276 ; free virtual = 45586 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 10270 ; free virtual = 45581 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 10266 ; free virtual = 45580 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 10264 ; free virtual = 45578 Phase 2 Final Placement Cleanup WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 10271 ; free virtual = 45581 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Starting Routing Task Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.277 ; gain = 511.531 ; free physical = 10273 ; free virtual = 45583 touch build/specimen_013/OK 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.277 ; gain = 577.562 ; free physical = 10279 ; free virtual = 45589 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_014 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 10159 ; free virtual = 45470 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10157 ; free virtual = 45467 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10153 ; free virtual = 45464 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10153 ; free virtual = 45463 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10153 ; free virtual = 45463 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10152 ; free virtual = 45463 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 10153 ; free virtual = 45464 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 10153 ; free virtual = 45463 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.559 ; gain = 248.945 ; free physical = 10118 ; free virtual = 45429 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 10087 ; free virtual = 45398 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10060 ; free virtual = 45371 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 10046 ; free virtual = 45357 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 10076 ; free virtual = 45386 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: Helper process launched with PID 27754 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9994 ; free virtual = 45305 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9980 ; free virtual = 45291 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9948 ; free virtual = 45259 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9940 ; free virtual = 45250 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9933 ; free virtual = 45244 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9933 ; free virtual = 45243 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9932 ; free virtual = 45243 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.582 ; gain = 269.969 ; free physical = 9952 ; free virtual = 45263 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.590 ; gain = 269.969 ; free physical = 9953 ; free virtual = 45263 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9926 ; free virtual = 45237 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9926 ; free virtual = 45237 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9926 ; free virtual = 45237 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9926 ; free virtual = 45236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9925 ; free virtual = 45236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9925 ; free virtual = 45236 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9924 ; free virtual = 45235 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9924 ; free virtual = 45234 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9925 ; free virtual = 45235 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 9832 ; free virtual = 45143 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9828 ; free virtual = 45139 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:744] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9436 ; free virtual = 44747 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9262 ; free virtual = 44573 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 9262 ; free virtual = 44573 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 9126 ; free virtual = 44437 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 1467.254 ; gain = 384.367 ; free physical = 8991 ; free virtual = 44302 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.957 ; gain = 0.000 ; free physical = 8989 ; free virtual = 44300 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1547.957 ; gain = 0.000 ; free physical = 8985 ; free virtual = 44296 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8856 ; free virtual = 44176 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 8904 ; free virtual = 44237 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8879 ; free virtual = 44212 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8877 ; free virtual = 44211 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27889 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 8842 ; free virtual = 44157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 8842 ; free virtual = 44156 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8332 ; free virtual = 43648 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 8353 ; free virtual = 43670 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8353 ; free virtual = 43669 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 972cf7e0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2057.926 ; gain = 93.668 ; free physical = 8366 ; free virtual = 43682 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 1335.062 ; gain = 239.152 ; free physical = 8370 ; free virtual = 43686 --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 972cf7e0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2063.914 ; gain = 99.656 ; free physical = 8354 ; free virtual = 43670 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 972cf7e0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2063.914 ; gain = 99.656 ; free physical = 8354 ; free virtual = 43671 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2129.957 ; gain = 30.758 ; free physical = 8363 ; free virtual = 43679 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Number of Nodes with overlaps = 0 Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.945 ; gain = 36.746 ; free physical = 8338 ; free virtual = 43656 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Phase 2 Router Initialization | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.945 ; gain = 36.746 ; free physical = 8338 ; free virtual = 43656 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 8338 ; free virtual = 43656 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8297 ; free virtual = 43632 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8293 ; free virtual = 43629 Phase 4 Rip-up And Reroute | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8293 ; free virtual = 43629 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8293 ; free virtual = 43629 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8292 ; free virtual = 43628 Phase 6 Post Hold Fix | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8292 ; free virtual = 43628 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.969 ; gain = 106.711 ; free physical = 8271 ; free virtual = 43607 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.969 ; gain = 109.711 ; free physical = 8268 ; free virtual = 43604 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 155c195dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.969 ; gain = 109.711 ; free physical = 8266 ; free virtual = 43601 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8293 ; free virtual = 43629 Phase 3 Initial Routing INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.969 ; gain = 109.711 ; free physical = 8300 ; free virtual = 43636 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2112.758 ; gain = 180.516 ; free physical = 8298 ; free virtual = 43634 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8293 ; free virtual = 43629 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8287 ; free virtual = 43623 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8287 ; free virtual = 43623 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8287 ; free virtual = 43623 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8286 ; free virtual = 43621 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 8287 ; free virtual = 43622 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8286 ; free virtual = 43622 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2112.758 ; gain = 0.000 ; free physical = 8265 ; free virtual = 43603 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8264 ; free virtual = 43601 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8255 ; free virtual = 43591 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8255 ; free virtual = 43591 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8255 ; free virtual = 43591 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8255 ; free virtual = 43591 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8255 ; free virtual = 43591 Phase 7 Route finalize INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8246 ; free virtual = 43581 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8262 ; free virtual = 43580 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 8260 ; free virtual = 43577 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 8258 ; free virtual = 43575 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8258 ; free virtual = 43574 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.000 ; gain = 55.801 ; free physical = 8289 ; free virtual = 43606 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2193.789 ; gain = 94.590 ; free physical = 8288 ; free virtual = 43605 INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8111 ; free virtual = 43435 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1344.094 ; gain = 248.184 ; free physical = 8110 ; free virtual = 43434 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 8081 ; free virtual = 43408 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:41 . Memory (MB): peak = 1344.094 ; gain = 248.184 ; free physical = 8079 ; free virtual = 43406 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 8038 ; free virtual = 43365 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7760 ; free virtual = 43094 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. INFO: [Timing 38-35] Done setting XDC timing constraints. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.789 ; gain = 0.000 ; free physical = 7783 ; free virtual = 43122 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7783 ; free virtual = 43123 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.445 ; gain = 0.000 ; free physical = 7715 ; free virtual = 43033 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7734 ; free virtual = 43053 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7724 ; free virtual = 43043 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7723 ; free virtual = 43041 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 7713 ; free virtual = 43031 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7704 ; free virtual = 43022 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 7632 ; free virtual = 42950 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7632 ; free virtual = 42950 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7635 ; free virtual = 42953 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7610 ; free virtual = 42928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7610 ; free virtual = 42928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7613 ; free virtual = 42931 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7623 ; free virtual = 42941 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 7624 ; free virtual = 42942 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7642 ; free virtual = 42960 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 7652 ; free virtual = 42970 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:37 ; elapsed = 00:00:44 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7652 ; free virtual = 42970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 7631 ; free virtual = 42949 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13f8005f1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 7630 ; free virtual = 42948 Running DRC as a precondition to command write_bitstream --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7577 ; free virtual = 42895 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7566 ; free virtual = 42884 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7562 ; free virtual = 42880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7545 ; free virtual = 42863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7541 ; free virtual = 42859 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.070 ; gain = 256.160 ; free physical = 7535 ; free virtual = 42853 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:45 . Memory (MB): peak = 1352.078 ; gain = 256.160 ; free physical = 7535 ; free virtual = 42853 INFO: [Project 1-571] Translating synthesized netlist Loading data files... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 7539 ; free virtual = 42857 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12bd49b1d Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.375 ; gain = 61.086 ; free physical = 7525 ; free virtual = 42843 Phase 3 Initial Routing WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2004.160 ; gain = 456.203 ; free physical = 7486 ; free virtual = 42804 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7478 ; free virtual = 42796 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7476 ; free virtual = 42794 Phase 4 Rip-up And Reroute | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7474 ; free virtual = 42792 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7473 ; free virtual = 42791 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7472 ; free virtual = 42790 Phase 6 Post Hold Fix | Checksum: 12bd49b1d Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7472 ; free virtual = 42790 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 7501 ; free virtual = 42819 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 7501 ; free virtual = 42819 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12bd49b1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 7499 ; free virtual = 42817 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 7537 ; free virtual = 42855 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2130.164 ; gain = 135.891 ; free physical = 7536 ; free virtual = 42854 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 7498 ; free virtual = 42820 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2004.160 ; gain = 456.203 ; free physical = 7325 ; free virtual = 42643 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 7350 ; free virtual = 42668 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2004.160 ; gain = 456.203 ; free physical = 7328 ; free virtual = 42647 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 188a0da2a --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 7268 ; free virtual = 42587 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2004.160 ; gain = 456.203 ; free physical = 7265 ; free virtual = 42584 Phase 2 Global Placement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 7108 ; free virtual = 42427 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2130.090 ; gain = 38.762 ; free physical = 6996 ; free virtual = 42315 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.078 ; gain = 44.750 ; free physical = 6970 ; free virtual = 42289 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.078 ; gain = 44.750 ; free physical = 6970 ; free virtual = 42289 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading data files... Phase 1 Build RT Design | Checksum: 18806395d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2068.961 ; gain = 42.668 ; free physical = 6952 ; free virtual = 42271 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18806395d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2075.949 ; gain = 49.656 ; free physical = 6913 ; free virtual = 42232 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18806395d Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2075.949 ; gain = 49.656 ; free physical = 6911 ; free virtual = 42230 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6907 ; free virtual = 42226 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:44 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6907 ; free virtual = 42225 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6859 ; free virtual = 42177 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6847 ; free virtual = 42166 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6849 ; free virtual = 42167 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: df19d8a1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.379 ; gain = 62.086 ; free physical = 6846 ; free virtual = 42164 Phase 3 Initial Routing --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6850 ; free virtual = 42169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6846 ; free virtual = 42165 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6845 ; free virtual = 42163 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 6842 ; free virtual = 42160 Synthesis Optimization Complete : Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 6842 ; free virtual = 42161 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6798 ; free virtual = 42117 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6799 ; free virtual = 42118 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6797 ; free virtual = 42115 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6797 ; free virtual = 42115 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6796 ; free virtual = 42115 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6797 ; free virtual = 42116 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6797 ; free virtual = 42116 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 6797 ; free virtual = 42115 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15b0a291a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 6796 ; free virtual = 42115 Number of Nodes with overlaps = 0 Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3 Initial Routing | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6797 ; free virtual = 42116 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15b0a291a Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 6765 ; free virtual = 42084 Phase 2.2 Pre Route Cleanup Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions.Phase 2.2 Pre Route Cleanup | Checksum: 15b0a291a South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 6765 ; free virtual = 42084 East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 4.1 Global Iteration 0 | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6759 ; free virtual = 42078 Phase 4 Rip-up And Reroute | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6759 ; free virtual = 42077 Phase 5 Delay and Skew Optimization Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6759 ; free virtual = 42077 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6758 ; free virtual = 42077 Phase 9 Depositing Routes Phase 5 Delay and Skew Optimization | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6757 ; free virtual = 42076 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6748 ; free virtual = 42067 Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6748 ; free virtual = 42067 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 6 Post Hold Fix | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6780 ; free virtual = 42099 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6780 ; free virtual = 42099 INFO: [Route 35-16] Router Completed Successfully Phase 3.2 Commit Most Macros & LUTRAMs Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2155.133 ; gain = 63.805 ; free physical = 6783 ; free virtual = 42102 Routing Is Done. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 6783 ; free virtual = 42102 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:50 . Memory (MB): peak = 2193.922 ; gain = 102.594 ; free physical = 6781 ; free virtual = 42100 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6769 ; free virtual = 42088 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.379 ; gain = 64.086 ; free physical = 6741 ; free virtual = 42061 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.379 ; gain = 66.086 ; free physical = 6735 ; free virtual = 42055 Phase 9 Depositing Routes Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 115f91288 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 6728 ; free virtual = 42047 Phase 3 Initial Routing Writing placer database... Phase 9 Depositing Routes | Checksum: df19d8a1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.379 ; gain = 66.086 ; free physical = 6713 ; free virtual = 42033 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.379 ; gain = 66.086 ; free physical = 6750 ; free virtual = 42070 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2131.168 ; gain = 136.891 ; free physical = 6749 ; free virtual = 42068 Writing placer database... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6713 ; free virtual = 42034 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6704 ; free virtual = 42026 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6691 ; free virtual = 42013 Phase 4 Rip-up And Reroute | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6691 ; free virtual = 42013 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6691 ; free virtual = 42013 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6691 ; free virtual = 42013 Phase 6 Post Hold Fix | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6689 ; free virtual = 42011 Phase 3.3 Area Swap Optimization Writing XDEF routing. Phase 7 Route finalize Writing XDEF routing logical nets. Writing XDEF routing special nets. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Write XDEF Complete: Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2131.168 ; gain = 0.000 ; free physical = 6665 ; free virtual = 41990 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 6663 ; free virtual = 41989 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6662 ; free virtual = 41988 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 115f91288 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6662 ; free virtual = 41987 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 6693 ; free virtual = 42019 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 6693 ; free virtual = 42019 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6693 ; free virtual = 42019 Phase 3.4 Pipeline Register Optimization Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 6691 ; free virtual = 42020 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6689 ; free virtual = 42019 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6690 ; free virtual = 42017 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6689 ; free virtual = 42015 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6689 ; free virtual = 42015 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6689 ; free virtual = 42016 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6689 ; free virtual = 42016 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6689 ; free virtual = 42015 Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6689 ; free virtual = 42015 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 6688 ; free virtual = 42013 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 6686 ; free virtual = 42012 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Loading route data... Processing options... Creating bitmap... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6382 ; free virtual = 41717 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6365 ; free virtual = 41703 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6349 ; free virtual = 41689 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.922 ; gain = 0.000 ; free physical = 6317 ; free virtual = 41660 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6326 ; free virtual = 41669 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6210 ; free virtual = 41553 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6254 ; free virtual = 41597 Phase 4.3 Placer Reporting INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.922 ; gain = 0.000 ; free physical = 6288 ; free virtual = 41609 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6294 ; free virtual = 41615 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6184 ; free virtual = 41505 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6110 ; free virtual = 41430 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2100.207 ; gain = 552.250 ; free physical = 6139 ; free virtual = 41459 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2100.207 ; gain = 632.953 ; free physical = 6140 ; free virtual = 41460 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading data files... Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 5947 ; free virtual = 41268 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing bitstream ./design.bit... Loading site data... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 6044 ; free virtual = 41369 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 6073 ; free virtual = 41398 Loading site data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Processing options... Creating bitmap... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:03:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2453.863 ; gain = 341.105 ; free physical = 5761 ; free virtual = 41086 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:03:59 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading data files... touch build/specimen_016/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_015 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Writing bitstream ./design.bit... INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:12 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 6634 ; free virtual = 41963 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:13 . Memory (MB): peak = 1476.828 ; gain = 393.945 ; free physical = 6897 ; free virtual = 42226 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Loading route data... Processing options... INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Creating bitmap... Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1 Placer Initialization Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 6550 ; free virtual = 41879 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.859 ; gain = 0.000 ; free physical = 6480 ; free virtual = 41809 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.89 . Memory (MB): peak = 1559.859 ; gain = 0.000 ; free physical = 6476 ; free virtual = 41805 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1554.859 ; gain = 0.000 ; free physical = 6482 ; free virtual = 41811 Loading site data... Loading route data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:04:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Processing options... Creating bitmap... 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2531.895 ; gain = 338.105 ; free physical = 6446 ; free virtual = 41775 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:04:07 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:04:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2467.270 ; gain = 337.105 ; free physical = 7898 ; free virtual = 43240 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:04:14 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:17 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 8905 ; free virtual = 44248 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:04:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2454.871 ; gain = 344.105 ; free physical = 8806 ; free virtual = 44149 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:04:15 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.859 ; gain = 0.000 ; free physical = 9497 ; free virtual = 44845 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.52 . Memory (MB): peak = 1558.859 ; gain = 0.000 ; free physical = 9486 ; free virtual = 44835 INFO: [Timing 38-35] Done setting XDC timing constraints. Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 9466 ; free virtual = 44816 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9676 ; free virtual = 45032 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9806 ; free virtual = 45163 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 9881 ; free virtual = 45238 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10024 ; free virtual = 45381 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10062 ; free virtual = 45419 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 10086 ; free virtual = 45443 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 10086 ; free virtual = 45443 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 10056 ; free virtual = 45413 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 10016 ; free virtual = 45373 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137cb3c3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 10016 ; free virtual = 45373 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 10015 ; free virtual = 45372 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 781ffd05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9990 ; free virtual = 45347 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9988 ; free virtual = 45345 Phase 4 Rip-up And Reroute | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9988 ; free virtual = 45345 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9988 ; free virtual = 45345 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9988 ; free virtual = 45345 Phase 6 Post Hold Fix | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9988 ; free virtual = 45345 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 9980 ; free virtual = 45337 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 9979 ; free virtual = 45336 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 781ffd05 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 9978 ; free virtual = 45335 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 10012 ; free virtual = 45369 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2109.766 ; gain = 177.516 ; free physical = 10012 ; free virtual = 45369 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 10009 ; free virtual = 45368 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:04:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.027 ; gain = 338.105 ; free physical = 9922 ; free virtual = 45280 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:04:22 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:04:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2470.273 ; gain = 339.105 ; free physical = 10923 ; free virtual = 46279 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:04:22 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_015/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29369 Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 15 #of bits: 43412 #of tags: 700 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Timing 38-35] Done setting XDC timing constraints. Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 11022 ; free virtual = 46386 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 10841 ; free virtual = 46205 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 10689 ; free virtual = 46053 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 10638 ; free virtual = 46002 Phase 1.3 Build Placer Netlist Model INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29514 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10476 ; free virtual = 45840 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 10362 ; free virtual = 45726 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 10342 ; free virtual = 45706 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 10305 ; free virtual = 45669 Phase 2 Final Placement Cleanup INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Phase 2 Final Placement Cleanup | Checksum: 208e4f915 WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 10285 ; free virtual = 45649 Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 10300 ; free virtual = 45664 Phase 1.4 Constrain Clocks/Macros WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 10241 ; free virtual = 45605 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 497.531 ; free physical = 10239 ; free virtual = 45603 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 10240 ; free virtual = 45605 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10219 ; free virtual = 45583 --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 10183 ; free virtual = 45547 Phase 2 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10108 ; free virtual = 45473 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10101 ; free virtual = 45466 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 10111 ; free virtual = 45475 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 10100 ; free virtual = 45464 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 492.531 ; free physical = 9993 ; free virtual = 45358 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 10023 ; free virtual = 45387 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading route data... INFO: Launching helper process for spawning children vivado processes Processing options... Creating bitmap... INFO: Helper process launched with PID 29589 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 9742 ; free virtual = 45106 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2128.965 ; gain = 28.758 ; free physical = 9747 ; free virtual = 45111 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2134.953 ; gain = 34.746 ; free physical = 9663 ; free virtual = 45028 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2134.953 ; gain = 34.746 ; free physical = 9661 ; free virtual = 45025 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: Launching helper process for spawning children vivado processes Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9587 ; free virtual = 44952 Phase 3 Initial Routing INFO: Helper process launched with PID 29624 Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9599 ; free virtual = 44964 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9597 ; free virtual = 44961 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9596 ; free virtual = 44961 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9597 ; free virtual = 44961 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9597 ; free virtual = 44961 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9597 ; free virtual = 44961 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Creating bitstream... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9566 ; free virtual = 44930 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9563 ; free virtual = 44928 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9555 ; free virtual = 44920 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2154.008 ; gain = 53.801 ; free physical = 9587 ; free virtual = 44951 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:47 . Memory (MB): peak = 2192.797 ; gain = 92.590 ; free physical = 9587 ; free virtual = 44952 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 9603 ; free virtual = 44969 Phase 1.3 Build Placer Netlist Model Writing placer database... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 9469 ; free virtual = 44850 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.797 ; gain = 0.000 ; free physical = 9534 ; free virtual = 44925 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:48] Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 9648 ; free virtual = 45018 Phase 1.4 Constrain Clocks/Macros WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:96] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:144] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9651 ; free virtual = 45021 WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:168] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2352] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2400] No constraint files found. INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 9677 ; free virtual = 45047 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 9674 ; free virtual = 45044 Running DRC as a precondition to command write_bitstream --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9658 ; free virtual = 45028 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 9652 ; free virtual = 45022 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 9642 ; free virtual = 45012 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 493.531 ; free physical = 9627 ; free virtual = 44997 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 9626 ; free virtual = 44996 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9547 ; free virtual = 44917 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9545 ; free virtual = 44915 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9541 ; free virtual = 44911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9539 ; free virtual = 44909 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9538 ; free virtual = 44908 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9537 ; free virtual = 44907 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9536 ; free virtual = 44906 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 9534 ; free virtual = 44904 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 9536 ; free virtual = 44906 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:04:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2451.871 ; gain = 342.105 ; free physical = 9468 ; free virtual = 44838 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:04:46 2019... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29734 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_018/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_017 INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29795 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 10173 ; free virtual = 45543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 10100 ; free virtual = 45471 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 10016 ; free virtual = 45387 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9968 ; free virtual = 45339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9961 ; free virtual = 45333 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9961 ; free virtual = 45333 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2] Loading data files... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 9875 ; free virtual = 45246 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 9760 ; free virtual = 45132 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 9765 ; free virtual = 45136 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/top.v:2] Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 9416 ; free virtual = 44787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 9473 ; free virtual = 44845 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9390 ; free virtual = 44763 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9422 ; free virtual = 44802 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 9405 ; free virtual = 44797 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9401 ; free virtual = 44793 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:48] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9377 ; free virtual = 44770 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 9366 ; free virtual = 44759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9366 ; free virtual = 44759 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9377 ; free virtual = 44751 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9377 ; free virtual = 44751 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 9376 ; free virtual = 44749 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9358 ; free virtual = 44732 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9357 ; free virtual = 44730 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9355 ; free virtual = 44729 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9355 ; free virtual = 44729 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9355 ; free virtual = 44728 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9354 ; free virtual = 44727 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9351 ; free virtual = 44725 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 9351 ; free virtual = 44724 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 9350 ; free virtual = 44723 INFO: [Project 1-571] Translating synthesized netlist Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 9015 ; free virtual = 44388 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 8981 ; free virtual = 44355 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.160 ; gain = 50.656 ; free physical = 8979 ; free virtual = 44353 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 8886 ; free virtual = 44260 Phase 3 Initial Routing INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/top.v:2] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8862 ; free virtual = 44236 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8860 ; free virtual = 44233 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8860 ; free virtual = 44233 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8859 ; free virtual = 44233 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8861 ; free virtual = 44234 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8862 ; free virtual = 44236 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 8899 ; free virtual = 44273 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 8899 ; free virtual = 44273 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.465 ; gain = 66.961 ; free physical = 8910 ; free virtual = 44284 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.465 ; gain = 66.961 ; free physical = 8946 ; free virtual = 44320 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2129.254 ; gain = 137.766 ; free physical = 8946 ; free virtual = 44320 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2129.254 ; gain = 0.000 ; free physical = 8897 ; free virtual = 44284 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 8853 ; free virtual = 44247 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 8829 ; free virtual = 44205 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 1336.066 ; gain = 240.152 ; free physical = 8951 ; free virtual = 44327 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1464.719 ; gain = 0.000 ; free physical = 8824 ; free virtual = 44220 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1464.719 ; gain = 0.000 ; free physical = 8824 ; free virtual = 44219 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 8784 ; free virtual = 44160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 8784 ; free virtual = 44160 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 8869 ; free virtual = 44249 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 8846 ; free virtual = 44226 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: synth_design -top top --------------------------------------------------------------------------------- Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1343.098 ; gain = 247.184 ; free physical = 8832 ; free virtual = 44212 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8823 ; free virtual = 44203 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1343.098 ; gain = 247.184 ; free physical = 8797 ; free virtual = 44177 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29989 Loading data files... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8699 ; free virtual = 44079 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8698 ; free virtual = 44078 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8697 ; free virtual = 44077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8697 ; free virtual = 44077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8696 ; free virtual = 44076 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8695 ; free virtual = 44075 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8694 ; free virtual = 44074 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 8689 ; free virtual = 44069 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 8690 ; free virtual = 44070 INFO: [Project 1-571] Translating synthesized netlist INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/top.v:2] --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 8680 ; free virtual = 44065 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:05:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Project 1-570] Preparing netlist for logic optimization 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2531.902 ; gain = 339.105 ; free physical = 8625 ; free virtual = 44023 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:05:13 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9470 ; free virtual = 44852 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 9474 ; free virtual = 44856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9450 ; free virtual = 44832 --------------------------------------------------------------------------------- touch build/specimen_016/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_018 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9471 ; free virtual = 44853 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9452 ; free virtual = 44847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9438 ; free virtual = 44840 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 9434 ; free virtual = 44835 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9430 ; free virtual = 44831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9424 ; free virtual = 44825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9422 ; free virtual = 44823 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1351.074 ; gain = 255.160 ; free physical = 9419 ; free virtual = 44820 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1351.082 ; gain = 255.160 ; free physical = 9421 ; free virtual = 44822 INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 9395 ; free virtual = 44797 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 9390 ; free virtual = 44793 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 9421 ; free virtual = 44823 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 9412 ; free virtual = 44814 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 9394 ; free virtual = 44796 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 9413 ; free virtual = 44796 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9412 ; free virtual = 44795 --------------------------------------------------------------------------------- Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 9409 ; free virtual = 44792 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 9408 ; free virtual = 44791 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 9305 ; free virtual = 44688 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 9252 ; free virtual = 44635 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 9235 ; free virtual = 44617 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 9235 ; free virtual = 44617 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 9232 ; free virtual = 44614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9120 ; free virtual = 44503 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 9120 ; free virtual = 44503 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9109 ; free virtual = 44492 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9043 ; free virtual = 44425 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9029 ; free virtual = 44412 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 9004 ; free virtual = 44387 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8997 ; free virtual = 44380 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8992 ; free virtual = 44374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8989 ; free virtual = 44372 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8989 ; free virtual = 44372 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 8989 ; free virtual = 44372 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 8991 ; free virtual = 44374 INFO: [Project 1-571] Translating synthesized netlist Loading site data... Phase 1 Build RT Design | Checksum: fa6cad5b Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2133.074 ; gain = 48.668 ; free physical = 8933 ; free virtual = 44316 Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] Phase 2 Router Initialization WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: fa6cad5b Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2143.602 ; gain = 59.195 ; free physical = 8851 ; free virtual = 44234 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: fa6cad5b Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2143.602 ; gain = 59.195 ; free physical = 8838 ; free virtual = 44221 Phase 1 Build RT Design | Checksum: 16930dc89 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.074 ; gain = 49.668 ; free physical = 8772 ; free virtual = 44155 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 19ba50c22 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8773 ; free virtual = 44156 Phase 3 Initial Routing Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 16930dc89 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8738 ; free virtual = 44121 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 16930dc89 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2144.062 ; gain = 59.656 ; free physical = 8737 ; free virtual = 44120 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 19ba50c22 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8727 ; free virtual = 44110 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8713 ; free virtual = 44095 Phase 4 Rip-up And Reroute | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8698 ; free virtual = 44081 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8689 ; free virtual = 44072 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8676 ; free virtual = 44059 Phase 6 Post Hold Fix | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8657 ; free virtual = 44040 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8610 ; free virtual = 43993 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8584 ; free virtual = 43967 Phase 9 Depositing Routes Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1065a9434 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8581 ; free virtual = 43964 Phase 3 Initial Routing INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1345.098 ; gain = 249.184 ; free physical = 8562 ; free virtual = 43945 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 19ba50c22 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8551 ; free virtual = 43934 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2197.531 ; gain = 113.125 ; free physical = 8594 ; free virtual = 43977 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2236.320 ; gain = 183.930 ; free physical = 8594 ; free virtual = 43977 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8583 ; free virtual = 43966 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 1345.098 ; gain = 249.184 ; free physical = 8573 ; free virtual = 43956 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8539 ; free virtual = 43922 Writing placer database... Phase 4 Rip-up And Reroute | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8526 ; free virtual = 43909 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8526 ; free virtual = 43911 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8550 ; free virtual = 43935 Phase 6 Post Hold Fix | Checksum: 1065a9434 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8545 ; free virtual = 43931 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1065a9434 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8525 ; free virtual = 43911 Phase 8 Verifying routed nets Verification completed successfully WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:16] Phase 8 Verifying routed nets | Checksum: 1065a9434 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8522 ; free virtual = 43909 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1065a9434 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8475 ; free virtual = 43865 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.992 ; gain = 95.586 ; free physical = 8516 ; free virtual = 43907 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2218.781 ; gain = 166.391 ; free physical = 8516 ; free virtual = 43906 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/top.v:2] Writing placer database... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8512 ; free virtual = 43913 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8482 ; free virtual = 43883 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 8335 ; free virtual = 43741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 8334 ; free virtual = 43741 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 8263 ; free virtual = 43673 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8532 ; free virtual = 43958 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8519 ; free virtual = 43945 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2236.320 ; gain = 0.000 ; free physical = 8401 ; free virtual = 43833 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 8399 ; free virtual = 43830 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8395 ; free virtual = 43826 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 8394 ; free virtual = 43826 --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 8394 ; free virtual = 43826 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 8394 ; free virtual = 43826 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 8394 ; free virtual = 43826 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 8396 ; free virtual = 43828 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 8396 ; free virtual = 43828 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8414 ; free virtual = 43847 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8492 ; free virtual = 43925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8489 ; free virtual = 43923 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8487 ; free virtual = 43921 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.074 ; gain = 257.160 ; free physical = 8488 ; free virtual = 43924 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:43 . Memory (MB): peak = 1353.082 ; gain = 257.160 ; free physical = 8490 ; free virtual = 43925 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2236.320 ; gain = 0.000 ; free physical = 8456 ; free virtual = 43870 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 8423 ; free virtual = 43840 --------------------------------------------------------------------------------- Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.781 ; gain = 0.000 ; free physical = 8420 ; free virtual = 43838 Phase 1 Build RT Design | Checksum: 169ce22cd Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.074 ; gain = 50.668 ; free physical = 8366 ; free virtual = 43788 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2218.781 ; gain = 0.000 ; free physical = 8381 ; free virtual = 43775 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:05:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2463.430 ; gain = 334.176 ; free physical = 8344 ; free virtual = 43737 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:05:32 2019... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 169ce22cd Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 8274 ; free virtual = 43668 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 169ce22cd Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2145.062 ; gain = 60.656 ; free physical = 8290 ; free virtual = 43684 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_019 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 178199bf5 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9205 ; free virtual = 44599 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9088 ; free virtual = 44482 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9087 ; free virtual = 44481 Phase 4 Rip-up And Reroute | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9086 ; free virtual = 44480 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9080 ; free virtual = 44474 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9077 ; free virtual = 44471 Phase 6 Post Hold Fix | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9070 ; free virtual = 44464 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 178199bf5 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9058 ; free virtual = 44452 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 178199bf5 Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9056 ; free virtual = 44450 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 178199bf5 Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9079 ; free virtual = 44474 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.992 ; gain = 96.586 ; free physical = 9123 ; free virtual = 44518 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 2219.781 ; gain = 167.391 ; free physical = 9123 ; free virtual = 44518 Writing placer database... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.207 ; gain = 0.000 ; free physical = 8741 ; free virtual = 44148 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8720 ; free virtual = 44128 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 8701 ; free virtual = 44111 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8651 ; free virtual = 44066 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 8608 ; free virtual = 44026 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 8603 ; free virtual = 44021 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 8603 ; free virtual = 44020 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 8603 ; free virtual = 44020 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 8602 ; free virtual = 44019 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 467.531 ; free physical = 8602 ; free virtual = 44019 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1931.250 ; gain = 533.562 ; free physical = 8602 ; free virtual = 44019 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30352 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.781 ; gain = 0.000 ; free physical = 8525 ; free virtual = 43948 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.832 ; gain = 393.945 ; free physical = 8485 ; free virtual = 43909 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8471 ; free virtual = 43896 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8465 ; free virtual = 43891 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2219.781 ; gain = 0.000 ; free physical = 8484 ; free virtual = 43883 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8482 ; free virtual = 43880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8478 ; free virtual = 43876 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8475 ; free virtual = 43873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8474 ; free virtual = 43872 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8474 ; free virtual = 43872 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 8472 ; free virtual = 43870 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 8472 ; free virtual = 43871 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1557.863 ; gain = 0.000 ; free physical = 8197 ; free virtual = 43595 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.79 . Memory (MB): peak = 1557.863 ; gain = 0.000 ; free physical = 8162 ; free virtual = 43560 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:11 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 7867 ; free virtual = 43266 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1558.863 ; gain = 0.000 ; free physical = 7560 ; free virtual = 42958 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 7566 ; free virtual = 42964 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1558.863 ; gain = 0.000 ; free physical = 7552 ; free virtual = 42950 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 7351 ; free virtual = 42749 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:10 . Memory (MB): peak = 1476.840 ; gain = 393.953 ; free physical = 7214 ; free virtual = 42612 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Loading site data... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 7157 ; free virtual = 42555 Loading route data... Loading site data... Processing options... Creating bitmap... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.61 . Memory (MB): peak = 1547.949 ; gain = 0.000 ; free physical = 7093 ; free virtual = 42492 Loading route data... Processing options... Creating bitmap... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7008 ; free virtual = 42407 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 7010 ; free virtual = 42409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 7018 ; free virtual = 42417 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1551.871 ; gain = 0.000 ; free physical = 7001 ; free virtual = 42401 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:01 . Memory (MB): peak = 1551.871 ; gain = 0.000 ; free physical = 6983 ; free virtual = 42382 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30527 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 6784 ; free virtual = 42184 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2068.176 ; gain = 44.668 ; free physical = 6555 ; free virtual = 41954 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 6506 ; free virtual = 41906 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 6493 ; free virtual = 41893 Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 6411 ; free virtual = 41810 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 6168 ; free virtual = 41568 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 6164 ; free virtual = 41564 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 6164 ; free virtual = 41563 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 6163 ; free virtual = 41562 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 6163 ; free virtual = 41562 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 6162 ; free virtual = 41561 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Loading site data... Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 6146 ; free virtual = 41545 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 6146 ; free virtual = 41545 Phase 9 Depositing Routes INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 6131 ; free virtual = 41531 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 6165 ; free virtual = 41565 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 6165 ; free virtual = 41564 Writing placer database... Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 6115 ; free virtual = 41517 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 6087 ; free virtual = 41488 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 6334 ; free virtual = 41738 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 6413 ; free virtual = 41817 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6358 ; free virtual = 41762 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 494.531 ; free physical = 6378 ; free virtual = 41785 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:36 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6386 ; free virtual = 41794 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6396 ; free virtual = 41803 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 6389 ; free virtual = 41797 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6483 ; free virtual = 41891 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6504 ; free virtual = 41913 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6532 ; free virtual = 41940 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6538 ; free virtual = 41946 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6540 ; free virtual = 41948 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 6551 ; free virtual = 41959 Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:37 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 6553 ; free virtual = 41961 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_016/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:06:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:45 . Memory (MB): peak = 2605.902 ; gain = 387.121 ; free physical = 6542 ; free virtual = 41950 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:06:17 2019... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. DONE WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Timing 38-35] Done setting XDC timing constraints. touch build/specimen_016/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_020 INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 7263 ; free virtual = 42671 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:06:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:49 . Memory (MB): peak = 2607.941 ; gain = 371.621 ; free physical = 7235 ; free virtual = 42644 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:06:20 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 494.531 ; free physical = 7342 ; free virtual = 42749 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 494.531 ; free physical = 8346 ; free virtual = 43753 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 494.531 ; free physical = 8321 ; free virtual = 43729 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 2052.395 ; gain = 494.531 ; free physical = 8248 ; free virtual = 43656 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed touch build/specimen_015/OK Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:38 . Memory (MB): peak = 2052.395 ; gain = 494.531 ; free physical = 8238 ; free virtual = 43646 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 8238 ; free virtual = 43646 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:16] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7926 ; free virtual = 43335 Phase 1.3 Build Placer Netlist Model INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/top.v:2] Phase 1 Build RT Design | Checksum: 10ee63a33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2056.934 ; gain = 92.668 ; free physical = 7813 ; free virtual = 43222 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10ee63a33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 7831 ; free virtual = 43240 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10ee63a33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 7832 ; free virtual = 43241 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.438 ; gain = 0.000 ; free physical = 7849 ; free virtual = 43264 Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 7865 ; free virtual = 43274 --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 162af8e98 Time (s): cpu = 00:00:40 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7865 ; free virtual = 43274 Phase 3 Initial Routing Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7848 ; free virtual = 43265 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7843 ; free virtual = 43262 Phase 4 Rip-up And Reroute | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7843 ; free virtual = 43261 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7843 ; free virtual = 43261 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7843 ; free virtual = 43261 Phase 6 Post Hold Fix | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 7843 ; free virtual = 43261 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 7887 ; free virtual = 43306 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7888 ; free virtual = 43308 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 162af8e98 Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7893 ; free virtual = 43312 INFO: [Route 35-16] Router Completed Successfully Starting Routing Task Time (s): cpu = 00:00:41 ; elapsed = 00:00:53 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 7933 ; free virtual = 43352 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 7936 ; free virtual = 43355 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 7959 ; free virtual = 43373 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 7964 ; free virtual = 43377 --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 8088 ; free virtual = 43503 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 7847 ; free virtual = 43261 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.359 ; gain = 0.000 ; free physical = 7777 ; free virtual = 43190 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 7734 ; free virtual = 43148 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7702 ; free virtual = 43116 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:36 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7687 ; free virtual = 43101 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7769 ; free virtual = 43183 Phase 2 Final Placement Cleanup 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:49 . Memory (MB): peak = 1468.246 ; gain = 385.359 ; free physical = 7775 ; free virtual = 43188 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7775 ; free virtual = 43188 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:37 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 7727 ; free virtual = 43140 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 7707 ; free virtual = 43120 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:06:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:47 . Memory (MB): peak = 2609.941 ; gain = 390.160 ; free physical = 7681 ; free virtual = 43095 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:06:28 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:34 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 8689 ; free virtual = 44101 Phase 1.4 Constrain Clocks/Macros Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Time (s): cpu = 00:00:19 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.402 ; gain = 500.531 ; free physical = 8721 ; free virtual = 44134 Phase 1.3 Build Placer Netlist Model Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 8716 ; free virtual = 44129 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.949 ; gain = 0.000 ; free physical = 8733 ; free virtual = 44146 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... touch build/specimen_017/OK Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:35 . Memory (MB): peak = 2003.152 ; gain = 455.203 ; free physical = 8733 ; free virtual = 44147 Phase 2 Global Placement Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1549.949 ; gain = 0.000 ; free physical = 8733 ; free virtual = 44146 Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Phase 1 Build RT Design | Checksum: 13e11bf6c Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2056.934 ; gain = 93.668 ; free physical = 8482 ; free virtual = 43896 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13e11bf6c Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2061.922 ; gain = 98.656 ; free physical = 8446 ; free virtual = 43859 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13e11bf6c Time (s): cpu = 00:00:40 ; elapsed = 00:00:51 . Memory (MB): peak = 2061.922 ; gain = 98.656 ; free physical = 8446 ; free virtual = 43859 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8408 ; free virtual = 43821 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 8400 ; free virtual = 43813 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4599df1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:52 . Memory (MB): peak = 2067.977 ; gain = 104.711 ; free physical = 8382 ; free virtual = 43795 Phase 3 Initial Routing Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8367 ; free virtual = 43781 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.402 ; gain = 500.531 ; free physical = 8317 ; free virtual = 43731 Phase 1.4 Constrain Clocks/Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8317 ; free virtual = 43730 Phase 3.2 Commit Most Macros & LUTRAMs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8293 ; free virtual = 43706 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8364 ; free virtual = 43777 Phase 4 Rip-up And Reroute | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8363 ; free virtual = 43776 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8363 ; free virtual = 43776 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8363 ; free virtual = 43776 Phase 6 Post Hold Fix | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:52 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8363 ; free virtual = 43776 Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.402 ; gain = 500.531 ; free physical = 8361 ; free virtual = 43775 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8347 ; free virtual = 43761 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 7 Route finalize | Checksum: b4599df1 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2068.977 ; gain = 105.711 ; free physical = 8347 ; free virtual = 43761 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2071.977 ; gain = 108.711 ; free physical = 8345 ; free virtual = 43758 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: b4599df1 Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2071.977 ; gain = 108.711 ; free physical = 8345 ; free virtual = 43759 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2071.977 ; gain = 108.711 ; free physical = 8378 ; free virtual = 43791 Phase 1 Placer Initialization | Checksum: 208e4f915 Routing Is Done. Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.402 ; gain = 500.531 ; free physical = 8377 ; free virtual = 43791 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully Phase 2 Final Placement Cleanup route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:55 . Memory (MB): peak = 2110.766 ; gain = 179.516 ; free physical = 8377 ; free virtual = 43791 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 8305 ; free virtual = 43719 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8293 ; free virtual = 43707 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.402 ; gain = 500.531 ; free physical = 8292 ; free virtual = 43707 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.402 ; gain = 500.531 ; free physical = 8361 ; free virtual = 43774 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:40 . Memory (MB): peak = 2052.402 ; gain = 575.562 ; free physical = 8352 ; free virtual = 43766 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Phase 3.3 Area Swap Optimization | Checksum: 23216312d Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Time (s): cpu = 00:00:29 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8334 ; free virtual = 43747 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:40 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8282 ; free virtual = 43695 Phase 3.5 Small Shape Detail Placement Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8297 ; free virtual = 43712 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8289 ; free virtual = 43704 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8275 ; free virtual = 43692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8283 ; free virtual = 43700 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8289 ; free virtual = 43706 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8289 ; free virtual = 43706 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8290 ; free virtual = 43707 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 8299 ; free virtual = 43716 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 8306 ; free virtual = 43724 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8578 ; free virtual = 43996 Phase 3.6 Re-assign LUT pins report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8586 ; free virtual = 44003 Phase 3.7 Pipeline Register Optimization Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:42 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8525 ; free virtual = 43943 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8513 ; free virtual = 43931 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8541 ; free virtual = 43959 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8455 ; free virtual = 43872 Phase 4.3 Placer Reporting INFO: [Project 1-570] Preparing netlist for logic optimization Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8414 ; free virtual = 43831 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8377 ; free virtual = 43794 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8343 ; free virtual = 43760 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:44 . Memory (MB): peak = 2099.199 ; gain = 551.250 ; free physical = 8319 ; free virtual = 43737 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 8317 ; free virtual = 43735 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:06:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2471.363 ; gain = 343.105 ; free physical = 8294 ; free virtual = 43711 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:06:39 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading data files... Loading site data... touch build/specimen_015/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 15 #of bits: 12552 #of tags: 110 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' Loading route data... Processing options... Creating bitmap... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitstream... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31650 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 9051 ; free virtual = 44473 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 8733 ; free virtual = 44155 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 8693 ; free virtual = 44115 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.438 ; gain = 0.000 ; free physical = 8651 ; free virtual = 44073 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:06:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2452.871 ; gain = 342.105 ; free physical = 8625 ; free virtual = 44047 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:06:48 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_019/OK Loading route data... Processing options... Creating bitmap... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 9502 ; free virtual = 44924 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 9485 ; free virtual = 44907 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 9416 ; free virtual = 44838 Phase 1.4 Constrain Clocks/Macros Writing bitstream ./design.bit... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 9501 ; free virtual = 44926 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.152 ; gain = 453.203 ; free physical = 9727 ; free virtual = 45153 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 9662 ; free virtual = 45088 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:16] Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 9658 ; free virtual = 45084 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/top.v:2] Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 9681 ; free virtual = 45107 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9678 ; free virtual = 45104 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:27 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 9689 ; free virtual = 45115 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:27 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 9683 ; free virtual = 45115 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 9682 ; free virtual = 45109 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 9682 ; free virtual = 45109 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:06:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2452.871 ; gain = 342.105 ; free physical = 9627 ; free virtual = 45054 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:06:56 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10592 ; free virtual = 46018 Phase 3.6 Re-assign LUT pins touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 1436 #of tags: 192 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10595 ; free virtual = 46021 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10587 ; free virtual = 46013 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10578 ; free virtual = 46004 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 10572 ; free virtual = 45998 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10571 ; free virtual = 45998 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10572 ; free virtual = 45998 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10569 ; free virtual = 45995 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10569 ; free virtual = 45995 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10568 ; free virtual = 45995 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.195 ; gain = 541.246 ; free physical = 10601 ; free virtual = 46027 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 2091.195 ; gain = 622.949 ; free physical = 10601 ; free virtual = 46027 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1a0edab69 Time (s): cpu = 00:00:39 ; elapsed = 00:00:36 . Memory (MB): peak = 2135.078 ; gain = 50.668 ; free physical = 10477 ; free virtual = 45903 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: 1a0edab69 Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 10441 ; free virtual = 45867 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a0edab69 Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2145.066 ; gain = 60.656 ; free physical = 10439 ; free virtual = 45866 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 10309 ; free virtual = 45735 --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 121342371 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10302 ; free virtual = 45728 Phase 3 Initial Routing Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 10225 ; free virtual = 45652 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10150 ; free virtual = 45577 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10173 ; free virtual = 45600 Phase 4 Rip-up And Reroute | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10172 ; free virtual = 45598 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10169 ; free virtual = 45595 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10162 ; free virtual = 45589 Phase 6 Post Hold Fix | Checksum: 121342371 Time (s): cpu = 00:00:41 ; elapsed = 00:00:37 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10165 ; free virtual = 45591 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 121342371 Time (s): cpu = 00:00:42 ; elapsed = 00:00:38 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10150 ; free virtual = 45577 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 121342371 Time (s): cpu = 00:00:42 ; elapsed = 00:00:38 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10136 ; free virtual = 45563 Phase 9 Depositing Routes INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10152 ; free virtual = 45579 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 121342371 Time (s): cpu = 00:00:42 ; elapsed = 00:00:38 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10150 ; free virtual = 45576 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:38 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 10198 ; free virtual = 45625 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:40 . Memory (MB): peak = 2218.785 ; gain = 166.391 ; free physical = 10199 ; free virtual = 45626 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 10201 ; free virtual = 45628 Writing placer database... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10173 ; free virtual = 45603 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10172 ; free virtual = 45603 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10171 ; free virtual = 45602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10170 ; free virtual = 45602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10170 ; free virtual = 45602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10170 ; free virtual = 45602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10170 ; free virtual = 45602 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 10171 ; free virtual = 45603 Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 10171 ; free virtual = 45603 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 10140 ; free virtual = 45581 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 16ac86fd8 Time (s): cpu = 00:00:37 ; elapsed = 00:00:33 . Memory (MB): peak = 2134.078 ; gain = 49.668 ; free physical = 10093 ; free virtual = 45538 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 16ac86fd8 Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 10014 ; free virtual = 45461 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 16ac86fd8 Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 2143.066 ; gain = 58.656 ; free physical = 10012 ; free virtual = 45461 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.785 ; gain = 0.000 ; free physical = 9979 ; free virtual = 45434 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e753ec2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9971 ; free virtual = 45426 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e753ec2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9949 ; free virtual = 45406 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9941 ; free virtual = 45399 Phase 4 Rip-up And Reroute | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9936 ; free virtual = 45394 Phase 5 Delay and Skew Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 5 Delay and Skew Optimization | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9962 ; free virtual = 45391 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 6.1 Hold Fix Iter | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9960 ; free virtual = 45389 Phase 6 Post Hold Fix | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9957 ; free virtual = 45387 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9929 ; free virtual = 45358 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9919 ; free virtual = 45348 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18e753ec2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9886 ; free virtual = 45315 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2177.996 ; gain = 93.586 ; free physical = 9936 ; free virtual = 45366 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:38 . Memory (MB): peak = 2216.785 ; gain = 164.391 ; free physical = 9939 ; free virtual = 45369 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 9956 ; free virtual = 45387 Phase 1.4 Constrain Clocks/Macros Writing placer database... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 9950 ; free virtual = 45383 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 9941 ; free virtual = 45376 Phase 2 Global Placement Phase 1 Build RT Design | Checksum: 19e9914bc Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 2134.086 ; gain = 49.668 ; free physical = 9850 ; free virtual = 45294 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19e9914bc Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 2145.074 ; gain = 60.656 ; free physical = 9826 ; free virtual = 45274 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19e9914bc Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 2145.074 ; gain = 60.656 ; free physical = 9825 ; free virtual = 45272 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2216.785 ; gain = 0.000 ; free physical = 9773 ; free virtual = 45231 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 197d64bf1 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9782 ; free virtual = 45240 Phase 3 Initial Routing Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9782 ; free virtual = 45240 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 197d64bf1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9778 ; free virtual = 45237 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9778 ; free virtual = 45237 Phase 3.2 Commit Most Macros & LUTRAMs Phase 4.1 Global Iteration 0 | Checksum: 197d64bf1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9776 ; free virtual = 45235 Phase 4 Rip-up And Reroute | Checksum: 197d64bf1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9775 ; free virtual = 45234 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 197d64bf1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9774 ; free virtual = 45233 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 197d64bf1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9773 ; free virtual = 45232 Phase 6 Post Hold Fix | Checksum: 197d64bf1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9772 ; free virtual = 45231 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 197d64bf1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9768 ; free virtual = 45227 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 197d64bf1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9765 ; free virtual = 45225 Phase 9 Depositing Routes Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9764 ; free virtual = 45225 Phase 3.3 Area Swap Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9783 ; free virtual = 45216 Phase 3.4 Pipeline Register Optimization Phase 9 Depositing Routes | Checksum: 197d64bf1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9763 ; free virtual = 45195 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9781 ; free virtual = 45214 Phase 3.5 Small Shape Detail Placement INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2181.504 ; gain = 97.086 ; free physical = 9803 ; free virtual = 45236 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:36 . Memory (MB): peak = 2220.293 ; gain = 167.891 ; free physical = 9801 ; free virtual = 45234 Writing placer database... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 9845 ; free virtual = 45282 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9744 ; free virtual = 45189 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9737 ; free virtual = 45183 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9694 ; free virtual = 45142 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9695 ; free virtual = 45145 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9704 ; free virtual = 45156 Phase 4.2 Post Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9772 ; free virtual = 45226 Phase 4.3 Placer Reporting Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1532.277 ; gain = 0.000 ; free physical = 9760 ; free virtual = 45215 Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9761 ; free virtual = 45216 Phase 4.4 Final Placement Cleanup Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1532.277 ; gain = 0.000 ; free physical = 9760 ; free virtual = 45216 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9758 ; free virtual = 45214 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9755 ; free virtual = 45212 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2220.293 ; gain = 0.000 ; free physical = 9821 ; free virtual = 45282 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.199 ; gain = 543.246 ; free physical = 9821 ; free virtual = 45282 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.199 ; gain = 623.949 ; free physical = 9821 ; free virtual = 45282 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2129.426 ; gain = 30.227 ; free physical = 9758 ; free virtual = 45219 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2136.414 ; gain = 37.215 ; free physical = 9738 ; free virtual = 45200 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:33 . Memory (MB): peak = 2136.414 ; gain = 37.215 ; free physical = 9740 ; free virtual = 45202 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:38 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9658 ; free virtual = 45094 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9641 ; free virtual = 45077 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9638 ; free virtual = 45074 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9637 ; free virtual = 45073 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9637 ; free virtual = 45073 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9637 ; free virtual = 45073 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9637 ; free virtual = 45073 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9676 ; free virtual = 45112 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9676 ; free virtual = 45112 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9688 ; free virtual = 45123 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:39 ; elapsed = 00:00:34 . Memory (MB): peak = 2154.469 ; gain = 55.270 ; free physical = 9727 ; free virtual = 45163 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:36 . Memory (MB): peak = 2193.258 ; gain = 94.059 ; free physical = 9730 ; free virtual = 45166 Writing placer database... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Loading data files... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.258 ; gain = 0.000 ; free physical = 9532 ; free virtual = 44991 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading data files... Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.766 ; gain = 0.000 ; free physical = 8066 ; free virtual = 43504 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... Loading route data... Processing options... Creating bitmap... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2003.480 ; gain = 471.203 ; free physical = 7975 ; free virtual = 43412 Phase 1.3 Build Placer Netlist Model Loading site data... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:35 . Memory (MB): peak = 2128.957 ; gain = 37.762 ; free physical = 7757 ; free virtual = 43195 Loading route data... Processing options... Creating bitmap... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:35 . Memory (MB): peak = 2135.945 ; gain = 44.750 ; free physical = 7705 ; free virtual = 43142 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:38 ; elapsed = 00:00:35 . Memory (MB): peak = 2135.945 ; gain = 44.750 ; free physical = 7705 ; free virtual = 43142 Loading site data... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.480 ; gain = 471.203 ; free physical = 7677 ; free virtual = 43115 Phase 1.4 Constrain Clocks/Macros Creating bitstream... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.480 ; gain = 471.203 ; free physical = 7661 ; free virtual = 43098 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:39 ; elapsed = 00:00:36 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7663 ; free virtual = 43100 Phase 3 Initial Routing Loading route data... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7652 ; free virtual = 43089 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.480 ; gain = 471.203 ; free physical = 7651 ; free virtual = 43088 Phase 2 Global Placement Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7651 ; free virtual = 43088 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7651 ; free virtual = 43088 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7651 ; free virtual = 43088 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7651 ; free virtual = 43088 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7651 ; free virtual = 43088 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Processing options... Creating bitmap... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7651 ; free virtual = 43088 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7650 ; free virtual = 43087 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7649 ; free virtual = 43086 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:37 . Memory (MB): peak = 2155.000 ; gain = 63.805 ; free physical = 7683 ; free virtual = 43121 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:38 . Memory (MB): peak = 2193.789 ; gain = 102.594 ; free physical = 7683 ; free virtual = 43120 Writing placer database... Creating bitstream... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.789 ; gain = 0.000 ; free physical = 8033 ; free virtual = 43497 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8043 ; free virtual = 43507 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8042 ; free virtual = 43507 Phase 3.2 Commit Most Macros & LUTRAMs Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8005 ; free virtual = 43449 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8163 ; free virtual = 43610 Phase 3.4 Pipeline Register Optimization Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8392 ; free virtual = 43838 Phase 3.5 Small Shape Detail Placement Writing bitstream ./design.bit... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8691 ; free virtual = 44142 Phase 3.6 Re-assign LUT pins INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8699 ; free virtual = 44150 Phase 3.7 Pipeline Register Optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8698 ; free virtual = 44148 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8674 ; free virtual = 44125 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8651 ; free virtual = 44102 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8720 ; free virtual = 44170 Phase 4.3 Placer Reporting INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:07:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:38 . Memory (MB): peak = 2607.945 ; gain = 389.160 ; free physical = 8721 ; free virtual = 44172 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:07:44 2019... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8723 ; free virtual = 44172 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 8773 ; free virtual = 44222 Creating bitstream... Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 9623 ; free virtual = 45072 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2107.531 ; gain = 575.254 ; free physical = 9859 ; free virtual = 45309 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2107.531 ; gain = 640.285 ; free physical = 9857 ; free virtual = 45307 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. touch build/specimen_018/OK INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_017/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:07:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2531.363 ; gain = 338.105 ; free physical = 9804 ; free virtual = 45255 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:07:45 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_017/OK WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:07:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:36 . Memory (MB): peak = 2607.945 ; gain = 391.160 ; free physical = 11062 ; free virtual = 46517 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:07:46 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_019/OK INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:07:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:01 ; elapsed = 00:00:35 . Memory (MB): peak = 2610.453 ; gain = 390.160 ; free physical = 12103 ; free virtual = 47558 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:07:49 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:36 ; elapsed = 00:00:35 . Memory (MB): peak = 2127.961 ; gain = 36.762 ; free physical = 13069 ; free virtual = 48523 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2133.949 ; gain = 42.750 ; free physical = 13035 ; free virtual = 48489 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2133.949 ; gain = 42.750 ; free physical = 13035 ; free virtual = 48489 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13022 ; free virtual = 48476 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13064 ; free virtual = 48518 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13063 ; free virtual = 48518 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13063 ; free virtual = 48518 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13063 ; free virtual = 48517 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13063 ; free virtual = 48517 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13063 ; free virtual = 48517 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13062 ; free virtual = 48516 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13060 ; free virtual = 48514 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13062 ; free virtual = 48516 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 13096 ; free virtual = 48550 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:38 . Memory (MB): peak = 2191.793 ; gain = 100.594 ; free physical = 13096 ; free virtual = 48550 Writing placer database... Creating bitstream... Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 39912 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2191.793 ; gain = 0.000 ; free physical = 13080 ; free virtual = 48558 Writing bitstream ./design.bit... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_018/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:07:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:16 . Memory (MB): peak = 2530.895 ; gain = 337.105 ; free physical = 13287 ; free virtual = 48747 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:07:57 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_018/OK Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2128.754 ; gain = 21.223 ; free physical = 14369 ; free virtual = 49833 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2135.742 ; gain = 28.211 ; free physical = 14338 ; free virtual = 49802 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2135.742 ; gain = 28.211 ; free physical = 14338 ; free virtual = 49802 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14367 ; free virtual = 49831 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14374 ; free virtual = 49838 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14374 ; free virtual = 49837 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14374 ; free virtual = 49837 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14374 ; free virtual = 49837 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14374 ; free virtual = 49837 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14374 ; free virtual = 49837 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14373 ; free virtual = 49837 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14372 ; free virtual = 49836 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14372 ; free virtual = 49836 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 2155.797 ; gain = 48.266 ; free physical = 14407 ; free virtual = 49871 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:22 . Memory (MB): peak = 2194.586 ; gain = 87.055 ; free physical = 14407 ; free virtual = 49871 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_019/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:08:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 2529.898 ; gain = 338.105 ; free physical = 14404 ; free virtual = 49882 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:08:07 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_019/OK Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2194.586 ; gain = 0.000 ; free physical = 15439 ; free virtual = 50925 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_020/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 08:08:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:14 . Memory (MB): peak = 2533.691 ; gain = 339.105 ; free physical = 15432 ; free virtual = 50901 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 08:08:22 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_020/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_016/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_019/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_015/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_020/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_018/segdata_tilegrid.txt. Reading build/specimen_017/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. Reading build/specimen_014/segdata_tilegrid.txt. Reading build/specimen_013/segdata_tilegrid.txt. #of segments: 20 #of bits: 6936 #of tags: 6650 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' Makefile:116: recipe for target 'run' failed make[1]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid'